公开(公告)号：US11416736B2

公开(公告)日：2022-08-16

申请号：US15855604

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kevin Nealis ,  Randy Huang

IPC: G06F7/523 ,  G06F7/544 ,  G06N3/063

Abstract: Systems and methods are related to improving throughput of neural networks in integrated circuits by combining values in operands to increase compute density. A system includes an integrated circuit (IC) having multiplier circuitry. The IC receives a first value and a second value in a first operand. The IC performs a multiplication operation, via the multiplier circuitry, on the first operand and a second operand to produce a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value.

公开(公告)号：US20180307975A1

公开(公告)日：2018-10-25

申请号：US15855604

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kevin Nealis ,  Randy Huang

IPC: G06N3/063 ,  G06F7/523 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F7/523 ,  G06F7/5443 ,  G06F2207/3828 ,  G06F2207/4824 ,  G06N3/08

Abstract: Systems and methods are related to improving throughput of neural networks in integrated circuits by combining values in operands to increase compute density. A system includes an integrated circuit (IC) having multiplier circuitry. The IC receives a first value and a second value in a first operand. The IC performs a multiplication operation, via the multiplier circuitry, on the first operand and a second operand to produce a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value.

公开(公告)号：US20180307783A1

公开(公告)日：2018-10-25

申请号：US15941983

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Vamsi Nalluri ,  Herman Henry Schmit ,  Scott J. Weber ,  Randy Huang

IPC: G06F17/50 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04

CPC classification number: G06F17/505 ,  G06N3/04 ,  G06N3/0635 ,  G06N3/08

Abstract: Systems and methods are included for efficiently implementing learned parameter systems (LPSs) on a programmable integrated circuit (PIC) via a computing engine. The computing engine receives an input set of learned parameters corresponding to use instances of an LPS. The computing engine reduces at least some redundancies and/or unnecessary operations using instance specific parameter values of the LPS, to generate a less redundant set of learned parameters and a corresponding less redundant LPS. The computing engine generates a netlist based on these, which may share computing resources of the PIC across multiple computations in accordance with the less redundant set of learned parameters and the corresponding less redundant LPS. The computing engine then programs the PIC with the netlist. That is, the netlist replaces use instances of at least some of the original learned parameters and its corresponding LPS and is executed instead of the original.

公开(公告)号：US10860760B2

公开(公告)日：2020-12-08

申请号：US15941983

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Vamsi Nalluri ,  Herman Henry Schmit ,  Scott J. Weber ,  Randy Huang

IPC: G06F30/327 ,  G06F30/34 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods are included for efficiently implementing learned parameter systems (LPSs) on a programmable integrated circuit (PIC) via a computing engine. The computing engine receives an input set of learned parameters corresponding to use instances of an LPS. The computing engine reduces at least some redundancies and/or unnecessary operations using instance specific parameter values of the LPS, to generate a less redundant set of learned parameters and a corresponding less redundant LPS. The computing engine generates a netlist based on these, which may share computing resources of the PIC across multiple computations in accordance with the less redundant set of learned parameters and the corresponding less redundant LPS. The computing engine then programs the PIC with the netlist. That is, the netlist replaces use instances of at least some of the original learned parameters and its corresponding LPS and is executed instead of the original.

公开(公告)号：US20180307438A1

公开(公告)日：2018-10-25

申请号：US15719922

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Randy Huang ,  Yeong Tat Liew ,  Jason Gee Hock Ong

IPC: G06F3/06 ,  G06F17/16 ,  G06F7/523 ,  G06F5/08 ,  G06F5/06 ,  G06F5/14 ,  G06F15/80

Abstract: A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.

公开(公告)号：US10585621B2

公开(公告)日：2020-03-10

申请号：US15719922

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Randy Huang ,  Yeong Tat Liew ,  Jason Gee Hock Ong

IPC: G06F17/30 ,  G06F3/06 ,  G06F17/16 ,  G06F7/523 ,  G06F5/08 ,  G06F5/06 ,  G06F15/80 ,  G06F5/14 ,  G06F15/76 ,  G06N3/063

Abstract: A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.