中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.074 seconds)

    SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFRESH ALGORITHM
    1.
    发明公开
    SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFRESH ALGORITHM 审中-公开

    公开(公告)号：US20240202124A1

    公开(公告)日：2024-06-20

    申请号：US18067779

    申请日：2022-12-19

    Applicant: Intel Corporation

    Inventor： Israel Diamand ,  Randy Osborne ,  Nadav Bonen

    IPC: G06F12/0831 ,  G06F12/0864

    CPC classification number: G06F12/0831 ,  G06F12/0864

    Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to computing systems implementing a very large cache for one or more processing engines in a shared memory system. According to various embodiments, a snoop filter tracks a hash value of the cached addresses instead of tracking the addresses themselves. Tracking hash values introduces inaccuracy and an inability to easily clean or refresh the snoop filter. A refresh algorithm maintains cache coherency without significant performance degradation. The cache refresh algorithm keeps the accuracy of the snoop filter, hence reducing the latency and power effects of false snoops. Further, the use of hash values reduces the hardware cost over traditional snoop filters.

    THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES
    2.
    发明申请
    THERMAL MANAGEMENT IN HORIZONTALLY OR VERTICALLY STACKED DIES 有权

    公开(公告)号：US20220300049A1

    公开(公告)日：2022-09-22

    申请号：US17203571

    申请日：2021-03-16

    Applicant: Intel Corporation

    Inventor： Somvir Singh Dahiya ,  Stephen Gunther ,  Julien Sebot ,  Randy Osborne ,  Scot Kellar ,  Joshua Een

    IPC: G06F1/20 ,  G06F1/3287 ,  G05B6/02

    Abstract: A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.

    Concurrent accesses of asymmetrical memory sources
    3.
    发明授权
    Concurrent accesses of asymmetrical memory sources 有权

    公开(公告)号：US10558570B2

    公开(公告)日：2020-02-11

    申请号：US15442470

    申请日：2017-02-24

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Zvika Greenfield ,  Randy Osborne

    IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0871 ,  G06F13/16

    Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

    ASYMMETRICAL MEMORY MANAGEMENT
    4.
    发明申请
    ASYMMETRICAL MEMORY MANAGEMENT 审中-公开

    公开(公告)号：US20170300415A1

    公开(公告)日：2017-10-19

    申请号：US15442470

    申请日：2017-02-24

    Applicant: Intel Corporation

    Inventor： Nadav BONEN ,  Zvika GREENFIELD ,  Randy Osborne

    IPC: G06F12/08 ,  G06F13/16

    Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

    Operating system transparent system memory abandonment
    6.
    发明授权
    Operating system transparent system memory abandonment 有权

    公开(公告)号：US10304418B2

    公开(公告)日：2019-05-28

    申请号：US15276856

    申请日：2016-09-27

    Applicant: Intel Corporation

    Inventor： Daniel Greenspan ,  Randy Osborne ,  Zvika Greenfield ,  Israel Diamand ,  Asaf Rubinstein

    IPC: G06F3/14 ,  G09G5/39 ,  G09G5/393 ,  G06F12/0895

    Abstract: An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.

Patent Agency Ranking