公开(公告)号：US12045909B2

公开(公告)日：2024-07-23

申请号：US17016126

申请日：2020-09-09

Applicant: Intel Corporation

Inventor： Venkataramani Gopalakrishnan ,  Ravishankar Subramanian ,  Shrestha Sinha ,  Duane Quiet ,  James Akiyama ,  Satish Ramanathan

IPC: G06F13/00 ,  G06F9/38 ,  G06F13/38 ,  G06F13/40 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F9/3877 ,  G06F13/382 ,  G06F13/4022 ,  G06F13/4027 ,  G06F2213/0038

Abstract: Embodiments are directed toward apparatuses, systems, and methods to implement policies for dynamically switching between an integrated graphics mode and a discrete graphics mode for providing a display signal to an external USB Type-C port. Some embodiments include a controller configured to provide signals to a first multiplexer and to a second multiplexer, and based on a platform policy, control the at least first or the second multiplexer to dynamically switch to the first graphics mode to output signals received from an integrated graphics controller to the external USB Type-C port or to switch to the second graphics mode to output signals received from a discrete graphics controller to the external USB Type-C port. Other embodiments may be described and/or claimed.

公开(公告)号：US20240330210A1

公开(公告)日：2024-10-03

申请号：US18192449

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Ravishankar Subramanian ,  Venkataramani Gopalakrishnan ,  Yaniv Hayat ,  Reuven Rozic

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/12 ,  G06F13/382 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0042

Abstract: Embodiments herein relate to reducing the power consumption of a serial link such as Peripheral Component Interconnect Express (PCIe) link. The link may extend between a System-On-A-Chip (SoC) or other circuit and a Universal Serial Bus (USB4) host in a computing device. The USB4 host includes a PCIe switch which connects lanes of the link to adapters in a USB4 router, such as a USB3 adapter, a PCIe adapter, a host interface adapter and a DisplayPort adapter. The available bandwidth of the link can be adjusted based on a measured data rate. For example, the data rate can be compared to one or more thresholds. In one approach, the data rate is based on downstream transmissions, from the SoC to the USB4 host. A transmitter clock rate can be adjusted to adjust the bandwidth and reduce power consumption.