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    Method and apparatus for performing a vector bit gather
    2.
    发明授权
    Method and apparatus for performing a vector bit gather 有权

    公开(公告)号：US10296334B2

    公开(公告)日：2019-05-21

    申请号：US14583639

    申请日：2014-12-27

    Applicant: INTEL CORPORATION

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal San Adrian ,  Mark J. Charney ,  Guillem Sole ,  Roger Espasa

    IPC: G06F9/30

    Abstract: Apparatus, method, and system for performing a vector bit gather are describe herein. One embodiment of a processor includes: a first vector register storing one or more source data elements, a second vector register storing one or more control elements, and a vector bit gather logic. Each of the control elements includes a plurality of bit fields, each of which is associated with a plurality of corresponding bit positions in a destination vector register and is to identify a bit from the one or more corresponding source data element to be copied to each of the plurality of corresponding bit positions. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a bit from the source data elements and responsively copy it to each of the plurality of corresponding bit positions in the destination vector register.

    BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    3.
    发明申请
    BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开

    公开(公告)号：US20170286112A1

    公开(公告)日：2017-10-05

    申请号：US15508284

    申请日：2015-09-04

    Applicant: Intel Corporation

    Inventor： Roger Espasa ,  Guillem Sole ,  David Guillen Fandos

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A processor includes packed data registers and a decode unit to decode an instruction. The instruction is to indicate a first source operand having at least one lane of bits, and a second source packed data operand having a number of sub-lane sized bit selection elements. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, stores a result operand in a destination storage location. The result operand includes, a different corresponding bit for each of the number of sub-lane sized bit selection elements. A value of each bit of the result operand corresponding to a sub-lane sized bit selection element is that of a bit of a corresponding lane of bits, of the at least one lane of bits of the first source operand, which is indicated by the corresponding sub-lane sized bit selection element.

    Method and apparatus for performing a vector bit shuffle
    4.
    发明授权
    Method and apparatus for performing a vector bit shuffle 有权

    公开(公告)号：US10296489B2

    公开(公告)日：2019-05-21

    申请号：US14583636

    申请日：2014-12-27

    Applicant: INTEL CORPORATION

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal San Adrian ,  Robert Valentine ,  Mark J. Charney ,  Guillem Sole ,  Roger Espasa

    IPC: G06F15/80 ,  G06F9/30

    Abstract: A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.

    BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    10.
    发明申请
    BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权

    公开(公告)号：US20210132950A1

    公开(公告)日：2021-05-06

    申请号：US16928501

    申请日：2020-07-14

    Applicant: Intel Corporation

    Inventor： Roger Espasa ,  Guillem Sole ,  David Guillen Fandos

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A processor includes packed data registers and a decode unit to decode an instruction. The instruction is to indicate a first source operand having at least one lane of bits, and a second source packed data operand having a number of sub-lane sized bit selection elements. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, stores a result operand in a destination storage location. The result operand includes, a different corresponding bit for each of the number of sub-lane sized bit selection elements. A value of each bit of the result operand corresponding to a sub-lane sized bit selection element is that of a bit of a corresponding lane of bits, of the at least one lane of bits of the first source operand, which is indicated by the corresponding sub-lane sized bit selection element.

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