公开(公告)号：US20230096451A1

公开(公告)日：2023-03-30

申请号：US17484193

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Salma Johnson ,  Duane Galbi ,  Bradley Burres ,  Jose Niell ,  Jeongnim Kim ,  Reshma Lal ,  Anandhi Jayakumar ,  Mrittika Ganguli ,  Thomas Willis

IPC: G06F9/50 ,  H04L29/08 ,  H04L29/06 ,  H04L9/08

Abstract: Techniques for remote disaggregated infrastructure processing units (IPUs) are described. An apparatus described herein includes an interconnect controller to receive a transaction layer packet (TLP) from a host compute node; identify a sender and a destination from the TLP; and provide, to a content addressable memory (CAM), a key determined from the sender and the destination. The apparatus as described herein can further include core circuitry communicably coupled to the interconnect controller, the core circuitry to determine an output of the CAM based on the key, the output comprising a network address of an infrastructure processing unit (IPU) assigned to the host compute node, wherein the IPU is disaggregated from the host compute node over a network; and send the TLP to the IPU using a transport protocol.

公开(公告)号：US20250036783A1

公开(公告)日：2025-01-30

申请号：US18915574

申请日：2024-10-15

Applicant: Intel Corporation

Inventor： Daniel Biederman ,  Yadong Li ,  Hemant Koka ,  Jackson Ellis ,  Salma Johnson

IPC: G06F21/60 ,  G06F21/78

Abstract: An apparatus is disclosed that includes a network interface device comprising processors to implement network interface device functionality and communication protocol engine circuitry, wherein the network interface device is to: receive a request to write data to a memory node communicably coupled to the network interface device; identify network information corresponding to the request, wherein the network information includes at least one of quality of service (QoS), physical function (PF), virtual function (VF), name space identifier (NSID), flow ID, service level objectives (SLOs), or process address space ID (PASID); identify characteristics of the memory node, wherein the characteristics include at least page size of the memory node; and cause the data to be coalesced with other data on the memory node based on the network information and the characteristics.

公开(公告)号：US20230342214A1

公开(公告)日：2023-10-26

申请号：US18345497

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Thomas E. Willis ,  Vered Bar Bracha ,  Dinesh Kumar ,  David Anderson ,  Dror Bohrer ,  Stephen Ibanez ,  Salma Johnson ,  Brad Burres

IPC: G06F9/50 ,  G06F9/54

CPC classification number: G06F9/505 ,  G06F9/547

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for a remote processing acceleration engine. Disclosed is an infrastructure processing unit (IPU) comprising an offload engine driver to access a remote procedure call (RPC) from business logic circuitry, network interface circuitry, and RPC offload circuitry to select a destination to perform an operation associated with the RPC call, the destination selected based on an ability of the destination to perform the operation using remote direct memory access (RDMA), and cause communication of the operation to the destination via the network interface circuitry.