公开(公告)号：US11669454B2

公开(公告)日：2023-06-06

申请号：US16405691

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Vedaraman Geetha ,  Jeffrey Baxter ,  Sai Prashanth Muralidhara ,  Sharada Venkateswaran ,  Daniel Liu ,  Nishant Singh ,  Bahaa Fahim ,  Samuel D. Strom

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.

公开(公告)号：US09405687B2

公开(公告)日：2016-08-02

申请号：US14070864

申请日：2013-11-04

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Samuel D. Strom ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Krishnakumar Ganapathy ,  Cesar Maldonado

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0831 ,  G06F12/0884 ,  G06F2212/2542 ,  Y02D10/13

Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括一个或多个核心和分布式缓存归属代理（包括与每个核心相关联的部分）。 每个部分包括高速缓存控制器，用于接收对数据的读取请求，并且响应于不存在于与高速缓存控制器相关联的高速缓冲存储器中的数据，向存储器控制器发出存储器请求以与 对归属代理的存储器请求，其中归属代理将从高速缓存控制器接收存储器请求并且为存储器请求保留条目。 描述和要求保护其他实施例。

公开(公告)号：US10339060B2

公开(公告)日：2019-07-02

申请号：US15396174

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Ashok Jagannathan ,  Jeffrey D. Chamberlain ,  Samuel D. Strom

IPC: G06F12/0817 ,  G06F12/0831

Abstract: System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.

公开(公告)号：US20180189180A1

公开(公告)日：2018-07-05

申请号：US15396174

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Ashok Jagannathan ,  Jeffrey D. Chamberlain ,  Samuel D. Strom

IPC: G06F12/0815

CPC classification number: G06F12/0833 ,  G06F12/0824 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.