公开(公告)号：US12204751B2

公开(公告)日：2025-01-21

申请号：US17359423

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Arvind Kumar ,  Dean-Dexter R. Eugenio ,  John R. Goles ,  Santhosh Muskula

IPC: G06F3/06 ,  G06N20/00

Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.

公开(公告)号：US12272426B2

公开(公告)日：2025-04-08

申请号：US17354788

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Arvind Kumar ,  Dean-Dexter R. Eugenio ,  Santhosh Muskula

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  H03K3/017 ,  H03K5/156

Abstract: Methods and apparatus for duty cycle adjuster optimization training algorithms to minimize jitter associated with DDR5 DRAM transmitters. Basic and Advanced Duty Cycle Adjuster (DCA) training algorithms are implemented to reduce duty cycle error and hence reduce phase mismatch translated jitter in the transmitter DQS signals. In accordance with aspects of the Basic DCA training algorithm, duty cycles for QCLK, IBQCLK, and QBCLK are adjusted by a memory controller that utilizes a DCA function implemented on a memory module (e.g., DDR5 SDRAM DIMM) to obtain a first set of optimized DCA code settings. The first set of optimized DCA code settings are then used as initial settings for the Advance DCA training algorithm to further optimize the DCA code settings for QCLK, IBQCLK, and QBCLK. A similar technical may be employed to reduce duty cycle error and jitter for DQ signals.