公开(公告)号：US20240053987A1

公开(公告)日：2024-02-15

申请号：US17887154

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah

IPC: G06F9/30

CPC classification number: G06F9/30141 ,  G06F9/3012

Abstract: An apparatus, system, and method for register file circuits are provided. A register file circuit can include a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, a second PMOS transistor including a source coupled to an output of the first inverter, and a second WBL (WBLB) coupled to a drain of the second PMOS transistor. 1R1W register file and 2R1W register file designs are provided.

公开(公告)号：US20240331761A1

公开(公告)日：2024-10-03

申请号：US18126680

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Amlan Ghosh ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah ,  Feroze Merchant

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

Abstract: An apparatus includes a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, and a second PMOS transistor including a source coupled to an output of the first inverter. The first PMOS transistor and the second PMOS transistor are disposed in at least one PMOS layer configured between a first metal layer and a second metal layer. The register file circuit further includes a first via connecting a gate of the first PMOS transistor and a gate of the second PMOS transistor in the at least one PMOS layer to the first metal layer.

公开(公告)号：US20230189495A1

公开(公告)日：2023-06-15

申请号：US17546770

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Seenivasan Subramaniam

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: Techniques are provided herein to form semiconductor devices having conductive backside structures to couple various transistor structures. In some embodiments, a given conductive backside structure acts as a shunt interconnect between two transistors, such as between the gate of one transistor and the source or drain region of another transistor. In an example, an integrated circuit includes two transistor devices having semiconductor material extending between separate source and drain regions and different gate structures over or around the semiconductor material of the two transistor devices. A conductive backside structure may be formed from the backside of the integrated circuit (e.g., after removing all or most of the substrate), where the backside structure contacts the source or drain region of one transistor and the gate structure of the other transistor.