公开(公告)号：US20190206782A1

公开(公告)日：2019-07-04

申请号：US15859331

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Siddarth KUMAR ,  Shawna M. LIFF

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.

公开(公告)号：US20250112174A1

公开(公告)日：2025-04-03

申请号：US18374618

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Siddarth KUMAR ,  Shripad GOKHALE ,  Edvin CETEGEN ,  Praneeth NAMPALLY ,  Astitva TRIPATHI ,  Sairam AGRAHARAM

IPC: H01L23/00 ,  H01L21/3205

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for forming an annealed shape metal alloy (SMA) on a wafer or a die complex. In embodiments, the annealed SMA, when heated above a transition temperature, may enter an Austenite phase and return to the shape that the wafer or die complex had when it was annealed. In embodiments, this may maintain a shape of a wafer or a die complex during higher temperature processing, for example during reflow, when the package undergoes fabrication. Other embodiments may be described and/or claimed.