公开(公告)号：US10771537B2

公开(公告)日：2020-09-08

申请号：US16023257

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Simon Perron Caissy ,  Carl Geoffrion ,  Eduardo Romero

IPC: H04L29/08 ,  H04L12/26 ,  H04L12/24

Abstract: Technologies for applying a scrambling function in unfair load balancing scenarios include a network device having a communication circuitry and compute engine executing software on the network device. The compute engine is to determine, using a load balancing function, a distribution for data sets to each of multiple bins. Each bin maps to a destination. The network device determines, as a function of the distribution, an unfairness score indicative of the distribution being unequal among each of the destinations. In response to a determination that the unfairness score exceeds a specified threshold, the network device enables a scrambling function to be performed during configuration of the plurality of bins with the destinations.

公开(公告)号：US20200007617A1

公开(公告)日：2020-01-02

申请号：US16023257

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Simon Perron Caissy ,  Carl Geoffrion ,  Eduardo Romero

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/26

Abstract: Technologies for applying a scrambling function in unfair load balancing scenarios include a network device having a communication circuitry and compute engine executing software on the network device. The compute engine is to determine, using a load balancing function, a distribution for data sets to each of multiple bins. Each bin maps to a destination. The network device determines, as a function of the distribution, an unfairness score indicative of the distribution being unequal among each of the destinations. In response to a determination that the unfairness score exceeds a specified threshold, the network device enables a scrambling function to be performed during configuration of the plurality of bins with the destinations.

公开(公告)号：US20240320100A1

公开(公告)日：2024-09-26

申请号：US18731175

申请日：2024-05-31

Applicant: Intel Corporation

Inventor： Robert Valiquette ,  Alexandre Hamel ,  Benoit Roy ,  Michel Noiseux ,  Simon Perron Caissy ,  Benjamin H. Shelton

IPC: G06F11/14 ,  H04L67/00 ,  H04L69/28

CPC classification number: G06F11/1438 ,  H04L67/34 ,  H04L69/28

Abstract: A warm restart is initiated at a network processor device, which includes a switch, one or more hardware components, and physical layer circuitry to implement one or more communication links. The switch is to be reset during the warm restart while the one or more communication links remain in an up state. A notification of the warm restart is sent to a set of drivers for the one or more hardware components and notifications are received from the set of drivers, where the notifications identify that reinitializations of the hardware components in association with the warm restart are complete. An indication is sent that the reinitializations of the hardware components are complete, where completion of the warm restart based on the indication.

公开(公告)号：US10965602B2

公开(公告)日：2021-03-30

申请号：US16353763

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Carl Geoffrion ,  Simon Perron Caissy ,  Eduardo L. Romero

IPC: H04L12/851 ,  G06F9/54 ,  H04L12/721 ,  H04L12/743 ,  H04L12/803 ,  H04L12/863 ,  H04L12/935

Abstract: Examples include a computing system having a load balancer circuitry to assign data units to destinations using a hash function having a plurality of hash bins, each hash bin being associated with a destination. The computing system includes a hash adjuster to assign a destination to each of the plurality of hash bins, sample assignment of data units to hash bins by the load balancer circuitry over a sample window, analyze the sampled assignments, and reassign destinations to the hash bins based at least in part on the analyzed sampled assignments. This results in increased system performance in processing of the data units by the load balancer.