公开(公告)号：US10795680B2

公开(公告)日：2020-10-06

申请号：US16289506

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Robert C. Valentine ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert D. Cavin ,  Bret L. Toll ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall ,  Dennis R. Bradford ,  Elmoustapha Ould-Ahmed-Vall ,  James C. Abel ,  Mark Charney ,  Seth Abraham ,  Suleyman Sair ,  Andrew Thomas Forsyth ,  Lisa Wu ,  Charles Yount

IPC: G06F9/30 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US09778909B2

公开(公告)日：2017-10-03

申请号：US15332721

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

IPC: G06F7/38 ,  G06F7/487 ,  G06F7/483 ,  G06F7/544 ,  G06F7/485 ,  G06F7/499

CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

公开(公告)号：US12231339B2

公开(公告)日：2025-02-18

申请号：US17093394

申请日：2020-11-09

Applicant: Intel Corporation

Inventor： Namrata Limaye ,  Venkata Suresh Kumar Paruchuri ,  Sridhar Samudrala ,  Kiran Patil

IPC: H04L47/125 ,  H04L47/11 ,  H04L47/22 ,  H04L47/2441

Abstract: Methods and apparatus for extending OpenvSwitch (OVS) megaflow offloads to hardware to address hardware pipeline limitations. Under a method implemented on a compute platform including a Network Interface Controller (NIC) having one or more ports and running software including OVS software and a Linux operating system having a kernel including a TC-flower module and a NIC driver a new megaflow is created with a mask in the OVS software employing a subset of microflow fields for a packet. The microflow fields and the megaflow mask is sent to the NIC driver. A new megaflow is implemented in the NIC driver employing a subset of the microflow fields and the NIC driver creates a new hardware flow on the NIC employing a packet match scheme using all the microflow fields. The NIC also programs a NIC hardware pipeline with the new hardware flow using a match scheme that may depend on the available hardware resources, such as the size of a TCAM.

公开(公告)号：US12170624B2

公开(公告)日：2024-12-17

申请号：US17492420

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Anjali Singhai Jain ,  Daniel Daly ,  Sridhar Samudrala ,  Linden Cornett ,  Phani Burra ,  Brett Creeley

IPC: H04L47/762 ,  H04L9/40 ,  H04L47/2425 ,  H04L47/78 ,  H04L47/80

Abstract: Examples described herein relate to one or more processors, when operational, to execute instructions stored in memory device, to cause performance of: execute a driver that is to: negotiate capabilities of hardware with a control plane for a virtualized execution environment and limit capabilities of the hardware available to the virtualized execution environment based on a service level agreement (SLA) associated with the virtualized execution environment. In some examples, the driver is to advertise hardware capabilities requested by the virtualized execution environment. In some examples, the control plane is to set capabilities of a hardware available to the virtualized execution environment based on the SLA.

公开(公告)号：US11740904B2

公开(公告)日：2023-08-29

申请号：US17524624

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Robert C. Valentine ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert D. Cavin ,  Bret L. Toll ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall ,  Dennis R. Bradford ,  Elmoustapha Ould-Ahmed-Vall ,  James C Abel ,  Mark Charney ,  Seth Abraham ,  Suleyman Sair ,  Andrew Thomas Forsyth ,  Lisa Wu ,  Charles Yount

IPC: G06F9/30 ,  G06F9/34 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696 ,  G06F9/30018 ,  H01L29/66

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US20180150654A1

公开(公告)日：2018-05-31

申请号：US15365119

申请日：2016-11-30

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Scott P. Dubal ,  Sridhar Samudrala ,  Praveen Mala ,  Sibai Li

IPC: G06F21/76 ,  H04L9/06

CPC classification number: G06F21/76 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/12 ,  H04L2209/76

Abstract: Examples include techniques for a field programmable gate array (FPGA) to perform one or more functions for an application specific integrated circuit (ASIC). Example techniques include communication between the ASIC and the FPGA via a sideband communication link to enable the ASIC to indicate to the FPGA a need for the FPGA to perform a function to fulfill a request received by the ASIC.

公开(公告)号：US20170039033A1

公开(公告)日：2017-02-09

申请号：US15332721

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

IPC: G06F7/487 ,  G06F7/499 ,  G06F7/544 ,  G06F7/485

CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

Abstract translation: 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

公开(公告)号：US20140281419A1

公开(公告)日：2014-09-18

申请号：US13840363

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Marc Lupon ,  Grigorios Magklis ,  Sridhar Samudrala ,  Raul Martinez ,  Kyriakos A. Stavrou ,  Enric Gibert Codina

IPC: G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/45508

Abstract: An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.

Abstract translation: 错误处理方法包括识别符合累积乘法（CMA）优化的代码区域并将代码区域指令转换为解释器代码指令，其可以包括将代码区域指令中的乘法加法指令的序列转换成包括CMA指令的融合代码。 可以监视由融合码产生的浮点（FP）异常，并且如果CMA中间舍入异常超过阈值，则可以重新转换码区指令的至少一部分以消除一些或全部融合码。

公开(公告)号：US12086594B2

公开(公告)日：2024-09-10

申请号：US18239106

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Robert C. Valentine ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert D. Cavin ,  Bret L. Toll ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall ,  Dennis R. Bradford ,  Elmoustapha Ould-Ahmed-Vall ,  James C Abel ,  Mark Charney ,  Seth Abraham ,  Suleyman Sair ,  Andrew Thomas Forsyth ,  Lisa Wu ,  Charles Yount

IPC: G06F9/30 ,  G06F9/34 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696 ,  G06F9/30018 ,  H01L29/66

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US11210096B2

公开(公告)日：2021-12-28

申请号：US17004711

申请日：2020-08-27

Applicant: Intel Corporation

Inventor： Robert C. Valentine ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert D. Cavin ,  Bret L. Toll ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall ,  Dennis R. Bradford ,  Elmoustapha Ould-Ahmed-Vall ,  James C Abel ,  Mark Charney ,  Seth Abraham ,  Suleyman Sair ,  Andrew Thomas Forsyth ,  Lisa Wu ,  Charles Yount

IPC: G06F9/30 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.