公开(公告)号：US20210019260A1

公开(公告)日：2021-01-21

申请号：US16986490

申请日：2020-08-06

Applicant: Intel Corporation

Inventor： Kyle Delehanty ,  Sridharan Sakthivelu ,  Janardhana Yoga Narasimhaswamy ,  Vijay Bahirji ,  Toby Opferman

IPC: G06F12/0846 ,  G06F12/0871 ,  G06F12/0806 ,  G06F9/50 ,  G06F9/455

Abstract: Systems, apparatuses and methods may provide for technology that identifies a NUMA node, defines a first virtual proximity domain within the NUMA node, and defines a second virtual proximity domain within the NUMA node, wherein the first virtual proximity domain and the second virtual proximity domain are defined via one or more OS interface tables.

公开(公告)号：US11989129B2

公开(公告)日：2024-05-21

申请号：US16986490

申请日：2020-08-06

Applicant: Intel Corporation

Inventor： Kyle Delehanty ,  Sridharan Sakthivelu ,  Janardhana Yoga Narasimhaswamy ,  Vijay Bahirji ,  Toby Opferman

IPC: G06F12/0846 ,  G06F9/455 ,  G06F9/50 ,  G06F12/0806 ,  G06F12/0871

CPC classification number: G06F12/0851 ,  G06F9/45533 ,  G06F9/5016 ,  G06F12/0806 ,  G06F12/0871 ,  G06F2009/45583 ,  G06F2212/2542

Abstract: Systems, apparatuses and methods may provide for technology that identifies a NUMA node, defines a first virtual proximity domain within the NUMA node, and defines a second virtual proximity domain within the NUMA node, wherein the first virtual proximity domain and the second virtual proximity domain are defined via one or more OS interface tables.

公开(公告)号：US10417218B2

公开(公告)日：2019-09-17

申请号：US14757602

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Kshitij A. Doshi ,  Sanjeev N. Trika ,  Sridharan Sakthivelu

IPC: G06F16/23 ,  G06F9/46

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receiving a sequence of transactions, each transaction including a request to write data to a memory device, processing the sequence of transactions, and communicating a response to a host after the sequence of transaction have been completed.

公开(公告)号：US09244839B2

公开(公告)日：2016-01-26

申请号：US14125741

申请日：2013-07-26

Applicant: Intel Corporation

Inventor： Sridharan Sakthivelu ,  Robert Bruce Bahnsen ,  Gerrit Saylor

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/126

Abstract: A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (WB-E) memory space for an application running on the processing unit. The memory management system maps the WB-E memory space to the persistent memory. The application creates WB-E data by executing an instruction to store data to an address in the WB-E memory space. The WB-E data is automatically stored in a cache associated with the processing unit in response to creation of the WB-E data by the application. In response to execution of a commit instruction by the application after the application has created WB-E data for multiple memory addresses, the memory management system automatically ensures that all of the WB-E data for the application has been saved to the persistent memory domain. Other embodiments are described and claimed.

Abstract translation: 处理设备具有处理单元，存储器管理系统和持久存储器域中的持久存储器。 处理设备为在处理单元上运行的应用提供增强的回写（WB-E）存储器空间。 存储器管理系统将WB-E存储器空间映射到持久存储器。 应用程序通过执行将数据存储到WB-E存储空间中的地址的指令来创建WB-E数据。 响应于应用程序创建WB-E数据，WB-E数据自动存储在与处理单元相关联的缓存中。 在应用程序创建了多个内存地址的WB-E数据之后，响应于应用程序执行提交指令，内存管理系统自动确保应用程序的所有WB-E数据都已保存到持久内存域 。 描述和要求保护其他实施例。