公开(公告)号：US11238155B2

公开(公告)日：2022-02-01

申请号：US16456578

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F9/38 ,  G06F21/55 ,  G06F21/62 ,  G06F9/48 ,  G06F12/0802

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US12032485B2

公开(公告)日：2024-07-09

申请号：US17133570

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Gilbert Neiger ,  Stephen Robinson ,  Dan Baum ,  Ron Gabor

IPC: G06F12/10 ,  G06F11/07 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F11/073 ,  G06F2212/657 ,  G06F2212/683

Abstract: Techniques to allow use of metadata in unused bits of virtual addresses are described. A processor of an aspect includes a decode circuit to decode a memory access instruction. The instruction to indicate one or more memory address operands that are to have address generation information and metadata. An execution circuit coupled with the decode circuit to generate a 64-bit virtual address based on the one or more memory address operands. The 64-bit virtual address having a bit 63, an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata. The execution circuit also to perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20220198023A1

公开(公告)日：2022-06-23

申请号：US17130722

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Ashwini Gopinath ,  Jason Brandt ,  Stephen Robinson

IPC: G06F21/57 ,  G06F9/455

Abstract: An embodiment of an apparatus includes memory to store a simulation model, a processor communicatively coupled to the memory, and logic communicatively coupled to the processor and the memory, the logic to run a simulation on the simulation model, identify one or more signals in the simulation model that contains data that should not be visible through any incidental channels, and selectively convert the identified one or more signals to an incidental-data state while the simulation runs. Other embodiments are disclosed and claimed.

公开(公告)号：US20220335126A1

公开(公告)日：2022-10-20

申请号：US17590470

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F21/55 ,  G06F21/62 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US20250053651A1

公开(公告)日：2025-02-13

申请号：US18925667

申请日：2024-10-24

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F21/55 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0802 ,  G06F21/62

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US12130915B2

公开(公告)日：2024-10-29

申请号：US17590470

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0802 ,  G06F21/55 ,  G06F21/62

CPC classification number: G06F21/556 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/30196 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/4881 ,  G06F12/0802 ,  G06F21/62

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor core includes an instruction fetch circuit to fetch instructions; a branch target buffer comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and a branch predictor, coupled to the instruction fetch circuit and the branch target buffer, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the branch target buffer, and cause the target instruction to be fetched by the instruction fetch circuit.