公开(公告)号：US10698432B2

公开(公告)日：2020-06-30

申请号：US13801777

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Yi-Chun Shih ,  Kaushik Mazumdar ,  Stephen T. Kim ,  Rinkle Jain ,  James W. Tschanz ,  Muhammad M. Khellah

IPC: G05F1/00 ,  G05F1/46 ,  H02M3/156 ,  G05F1/563

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

公开(公告)号：US09766827B1

公开(公告)日：2017-09-19

申请号：US15151402

申请日：2016-05-10

Applicant: Intel Corporation

Inventor： Pascal A. Meinerzhagen ,  Stephen T. Kim ,  Anupama A. Thaploo ,  Muhammad M. Khellah

IPC: G05F1/613 ,  G06F3/06 ,  G11C5/14

CPC classification number: G11C5/148

Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

公开(公告)号：US11921529B2

公开(公告)日：2024-03-05

申请号：US16914174

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Yi-Chun Shih ,  Kaushik Mazumdar ,  Stephen T. Kim ,  Rinkle Jain ,  James W. Tschanz ,  Muhammad M. Khellah

IPC: G05F1/46 ,  G05F1/56 ,  G05F1/563 ,  H02M3/15 ,  G05F1/00 ,  H02M3/156

CPC classification number: G05F1/563 ,  G05F1/46 ,  G05F1/00 ,  H02M3/156

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

公开(公告)号：US10418076B2

公开(公告)日：2019-09-17

申请号：US15706521

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Pascal A. Meinerzhagen ,  Stephen T. Kim ,  Anupama A. Thaploo ,  Muhammad M. Khellah

IPC: G11C5/14

Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.