公开(公告)号：US12086591B2

公开(公告)日：2024-09-10

申请号：US17214698

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Sudhanshu Shukla ,  Jayesh Gaur ,  Stanislav Shwartsman ,  Pavel I. Kryukov

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3856

Abstract: Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.

公开(公告)号：US20220308876A1

公开(公告)日：2022-09-29

申请号：US17214698

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Sudhanshu Shukla ,  Jayesh Gaur ,  Stanislav Shwartsman ,  Pavel I. Kryukov

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.

公开(公告)号：US11043256B2

公开(公告)日：2021-06-22

申请号：US16458022

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Huichu Liu ,  Tanay Karnik ,  Sreenivas Subramoney ,  Jayesh Gaur ,  Sudhanshu Shukla

IPC: G11C11/4096 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/22

Abstract: Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) may be read, by walking through column multiplexor addresses (instead of just reading out one column multiplexor address per WL fire or memory access). The mechanisms and methods disclosed herein may advantageously enable N distinct memory words to be read out if the array uses an N-to-1 column multiplexor. Since memories such as embedded DRAMs (eDRAMs) may undergo a destructive read, for a given WL fire, a design may be disposed to sense N distinct memory words and restore them in order.