公开(公告)号：US20230099989A1

公开(公告)日：2023-03-30

申请号：US17484969

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sundararajan Ramakrishnan ,  Jonathan Combs ,  Martin J. Licht ,  Santhosh Srinath

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/07

Abstract: Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to: determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster, track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.

公开(公告)号：US12254319B2

公开(公告)日：2025-03-18

申请号：US17484969

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sundararajan Ramakrishnan ,  Jonathan Combs ,  Martin J. Licht ,  Santhosh Srinath

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/07

Abstract: Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to: determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster, track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.