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    Stubby pads for channel cross-talk reduction
    1.
    发明授权
    Stubby pads for channel cross-talk reduction 有权
    短路焊盘，用于通道串扰降低

    公开(公告)号：US09105635B2

    公开(公告)日：2015-08-11

    申请号：US13801998

    申请日：2013-03-13

    Applicant: INTEL CORPORATION

    Inventor： Nevin Altunyurt ,  Tolga Memioglu ,  Kemal Aygun

    IPC: H01L23/498 ,  H01L23/522 ,  H01L23/66

    CPC classification number: H01L23/5226 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/642 ,  H01L23/66 ,  H01L2223/6633 ,  H01L2224/16237 ,  H01L2224/16265 ,  H01L2224/16267 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 μm) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 μm), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC.

    Abstract translation: 金属表面特征，例如衬垫，终止垂直过渡通过诸如IC封装衬底的衬底的一个或多个衬底，其提供高边缘表面积以与相邻金属表面特征上的一个或多个互补短截线耦合的短截线 提供期望量的互电容，其可以至少部分地消除整个信道串扰（例如，FEXT）减少的串扰。 在实施例中，为多于两个焊盘提供相邻焊盘的​​电容耦合以实现多于一个受害者 - 侵略者对的串扰减少和/或实现两个以上侵略者的串扰减少。 在实施例中，焊盘具有适于与插入件或PCB插座对接的大间距（例如，1000μm），而短截线之间的间隙较小（例如，15μm），仅受金属允许的最小间隔的限制 用于与IC连接的封装的相对侧的特征。

    Coupled vias for channel cross-talk reduction
    2.
    发明授权
    Coupled vias for channel cross-talk reduction 有权

    公开(公告)号：US10103054B2

    公开(公告)日：2018-10-16

    申请号：US13802011

    申请日：2013-03-13

    Applicant: INTEL CORPORATION

    Inventor： Zhichao Zhang ,  Zhiguo Qian ,  Tolga Memioglu ,  Kemal Aygun

    IPC: H05K7/10 ,  H05K7/12 ,  H01L21/768 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50

    Abstract: Capacitively coupled vertical transitions are configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.

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