公开(公告)号：US12130738B2

公开(公告)日：2024-10-29

申请号：US17130632

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jayesh Gaur ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Utkarsh Kakaiya

IPC: G06F12/0802 ,  H03M7/30

CPC classification number: G06F12/0802 ,  H03M7/60 ,  G06F2212/401 ,  G06F2212/60

Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.

公开(公告)号：US20230185603A1

公开(公告)日：2023-06-15

申请号：US17551166

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Saurabh Gayen ,  Philip Lantz ,  Narayan Ranganathan ,  Dhananjay Joshi ,  Rajesh Sankaran ,  Utkarsh Kakaiya

IPC: G06F9/48 ,  G06Q30/02

CPC classification number: G06F9/4881 ,  G06Q30/0283

Abstract: Methods and apparatus relating to dynamic capability discovery and enforcement for accelerators and devices in multi-tenant systems are described. In an embodiment, a hardware accelerator device advertises one or more available operations and/or capabilities of the hardware accelerator device to one or more tenants. Logic circuitry controls access to the one or more available operations and/or capabilities of the one or more work queues on a per-tenant basis. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220197793A1

公开(公告)日：2022-06-23

申请号：US17130632

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jayesh Gaur ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Utkarsh Kakaiya

IPC: G06F12/0802

Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.

公开(公告)号：US11372787B2

公开(公告)日：2022-06-28

申请号：US15836854

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Utkarsh Kakaiya ,  Nagabhushan Chitlur ,  Rajesh M. Sankaran ,  Mohan Nair ,  Pratik M. Marolia

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42 ,  G06F12/10 ,  G06F12/1036

Abstract: There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.

公开(公告)号：US20210026543A1

公开(公告)日：2021-01-28

申请号：US17032789

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Anna Trikalinou ,  Ramya Jayaram Masti ,  Utkarsh Kakaiya ,  David Koufaty ,  Vedvyas Shanbhogue

IPC: G06F3/06

Abstract: An apparatus to facilitate security of a shared memory resource is disclosed. The apparatus includes a memory device to store memory data a system agent to receive requests from one or more input/output (I/O) devices to access the memory data memory and trusted translation components having trusted host physical address (HPA) permission tables (HPTs) to validate memory address translation requests received from trusted I/O devices to access pages in memory associated with trusted domains.

公开(公告)号：US20190034367A1

公开(公告)日：2019-01-31

申请号：US15836854

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Utkarsh Kakaiya ,  Nagabhushan Chitlur ,  Rajesh M. Sankaran ,  Mohan Nair ,  Pratik M. Marolia

IPC: G06F13/20 ,  G06F13/40

Abstract: There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.