公开(公告)号：US11237840B2

公开(公告)日：2022-02-01

申请号：US16091201

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Myles Wilde ,  Michael F. Fallon ,  Amit Kumar ,  Chengda Yang ,  Aaron Gorius ,  William R. Wheeler

IPC: G06F9/00 ,  G06F9/4401 ,  G06F1/16 ,  G06F13/40 ,  G06K19/04

Abstract: All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device. The all in one device has a form factor that is approximately the size of a credit card, yet is capable of running a full-fledged desktop operating system.

公开(公告)号：US10922148B2

公开(公告)日：2021-02-16

申请号：US16091206

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Myles Wilde ,  William R. Wheeler ,  Michael F. Fallon ,  Aaron Gorius ,  Amit Kumar ,  Chengda Yang

IPC: G06F9/54 ,  G06F9/451 ,  G06F9/445 ,  G06F13/12 ,  G06F13/38 ,  G06F9/48 ,  G06F13/362 ,  G06F13/42

Abstract: Techniques for implementing assess to Android applications and native Window application on Android devices and systems. A processor board includes a processor that is configured to run a full version of a Windows operating system and Windows applications. The processor board is configured to be communicatively coupled to the processor board in an Android device, such as a Smartphone or tablet. Upon operations and when the processor board is communicatively coupled to the Android device, a user of the Android device is enabled to selectively run Android applications and Windows applications, with the Windows applications being executed natively on the processor board. The processor board may be implemented in a computing card that is approximately the size of a credit card or smaller, which in turn may be coupled to the Android device via a backpack or similar means. The processor board may also be disposed within the same housing as the Android device.

公开(公告)号：US10761979B2

公开(公告)日：2020-09-01

申请号：US15201303

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Hugh Wilkinson ,  William R. Wheeler ,  Debra Bernstein

IPC: G06F12/02 ,  G06F9/30 ,  G11C7/10

Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20200326955A1

公开(公告)日：2020-10-15

申请号：US16091201

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Myles Wilde ,  Michael F. Fallon ,  Amit Kumar ,  Chengda Yang ,  Aaron Gorius ,  William R. Wheeler

IPC: G06F9/4401 ,  G06F13/40 ,  G06K19/04 ,  G06F1/16

Abstract: All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device. The all in one device has a form factor that is approximately the size of a credit card, yet is capable of running a full-fledged desktop operating system.

公开(公告)号：US20200082782A1

公开(公告)日：2020-03-12

申请号：US16576386

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Myles Wilde ,  Matthew J. Adiletta ,  William R. Wheeler ,  Michael F. Fallon ,  Thomas M. Garrison ,  Aaron Gorius ,  Chengda Yang

IPC: G09G5/00 ,  H04W4/18 ,  H04N5/38 ,  G06T1/60 ,  H04N19/44 ,  H04N19/423 ,  H04W76/14 ,  H04W4/80 ,  H04W4/21 ,  H04L29/06 ,  G06F13/38 ,  H04W12/00

Abstract: Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.

公开(公告)号：US20190121682A1

公开(公告)日：2019-04-25

申请号：US16091206

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Myles Wilde ,  William R. Wheeler ,  Michael F. Fallon ,  Aaron Gorius ,  Amit Kumar ,  Chengda Yang

IPC: G06F9/54 ,  G06F13/42 ,  G06F13/362 ,  G06F9/48 ,  G06F9/451

Abstract: Techniques for implementing assess to Android applications and native Window application on Android devices and systems. A processor board includes a processor that is configured to run a full version of a Windows operating system and Windows applications. The processor board is configured to be communicatively coupled to the processor board in an Android device, such as a Smartphone or tablet. Upon operations and when the processor board is communicatively coupled to the Android device, a user of the Android device is enabled to selectively run Android applications and Windows applications, with the Windows applications being executed natively on the processor board. The processor board may be implemented in a computing card that is approximately the size of a credit card or smaller, which in turn may be coupled to the Android device via a backpack or similar means. The processor board may also be disposed within the same housing as the Android device.

公开(公告)号：US20180095892A1

公开(公告)日：2018-04-05

申请号：US15283355

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Hugh Wilkinson ,  William R. Wheeler ,  Shirish Aundhe ,  Sandhya Viswanathan ,  David A. Koufaty

IPC: G06F12/1027 ,  G06F12/14 ,  G06F9/30

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30145 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/68

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20180004655A1

公开(公告)日：2018-01-04

申请号：US15201303

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Hugh Wilkinson ,  William R. Wheeler ,  Debra Bernstein

IPC: G06F12/02 ,  G11C7/10

Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.