公开(公告)号：US20240104025A1

公开(公告)日：2024-03-28

申请号：US17951914

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Biju George ,  Zamshed I. Chowdhury ,  Prathamesh Raghunath Shinde ,  Chunhui Mei ,  Fangwen Fu

IPC: G06F12/123 ,  G06F12/0862

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F2212/1021

Abstract: Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.