公开(公告)号：US12199629B2

公开(公告)日：2025-01-14

申请号：US18107219

申请日：2023-02-08

Applicant: InvenSense, Inc.

Inventor： Omid Oliaei ,  Aurelio Pellegrini ,  Daniele Ottini

IPC: H03M1/10 ,  H03M3/00 ,  H03K19/20

Abstract: A circuit for a feedback system incorporates a gating mechanism to reduce flicker noise (e.g., a source for bias instability within a MEMS device) at a digital output. The gating mechanism generates a gating pulse with a delay period (e.g., a common, or fixed, delay including symmetrical rising and falling edge delays) that overrides internal delays (e.g., asymmetrical rising and falling edge delays) of a phase generator to prevent propagation delay (e.g., delay affected by jitter) from reaching subsequent feedback components (e.g., a digital-to-analog converter (DAC)) and contributing to the generation of flicker noise within the system.

公开(公告)号：US20240267055A1

公开(公告)日：2024-08-08

申请号：US18107219

申请日：2023-02-08

Applicant: InvenSense, Inc.

Inventor： Omid Oliaei ,  Aurelio Pellegrini ,  Daniele Ottini

IPC: H03M1/10 ,  H03M3/00

CPC classification number: H03M1/1071 ,  H03M3/458 ,  H03K19/20

Abstract: A circuit for a feedback system incorporates a gating mechanism to reduce flicker noise (e.g., a source for bias instability within a MEMS device) at a digital output. The gating mechanism generates a gating pulse with a delay period (e.g., a common, or fixed, delay including symmetrical rising and falling edge delays) that overrides internal delays (e.g., asymmetrical rising and falling edge delays) of a phase generator to prevent propagation delay (e.g., delay affected by jitter) from reaching subsequent feedback components (e.g., a digital-to-analog converter (DAC)) and contributing to the generation of flicker noise within the system.