公开(公告)号：US20140339550A1

公开(公告)日：2014-11-20

申请号：US14359262

申请日：2012-10-23

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Tatsuya Shimoda ,  Takaaki Miyasako ,  Eisuke Tokumitsu ,  Bui Nguyen Quoc Trinh

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/24 ,  H01L21/02

CPC classification number: H01L29/516 ,  C01G25/00 ,  C01G25/006 ,  C01G29/006 ,  C01G35/00 ,  C01P2002/85 ,  C01P2004/04 ,  H01L21/02192 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/02282 ,  H01L28/55 ,  H01L28/56 ,  H01L28/75 ,  H01L29/24 ,  H01L29/40111 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78391 ,  H01L29/7869 ,  H01L41/0478 ,  H01L41/0805

Abstract: Provided is a ferroelectric gate thin film transistor which includes: a channel layer; a gate electrode layer which controls a conductive state of the channel layer; and a gate insulation layer which is arranged between the channel layer and the gate electrode layer and is formed of a ferroelectric layer. The gate insulation layer (ferroelectric layer) has the structure where a PZT layer and a BLT layer (Pb diffusion preventing layer) are laminated to each other. The channel layer (oxide conductor layer) is arranged on a surface of the gate insulation layer (ferroelectric layer) on a BLT layer (Pb diffusion preventing layer) side. The ferroelectric gate thin film transistor can overcome various drawbacks which may be caused due to the diffusion of Pb atoms into an oxide conductor layer from a PZT layer including a drawback that a transmission characteristic of a ferroelectric gate thin film transistor is liable to be deteriorated (for example, a width of a memory window is liable to become narrow).

Abstract translation: 提供一种铁电栅极薄膜晶体管，其包括：沟道层; 栅极电极层，其控制沟道层的导电状态; 以及栅极绝缘层，其布置在沟道层和栅电极层之间并且由铁电层形成。 栅绝缘层（铁电体层）具有将PZT层和BLT层（Pb扩散防止层）层叠的结构。 沟道层（氧化物导体层）配置在BLT层（Pb扩散防止层）侧的栅极绝缘层（铁电体层）的表面。 铁电栅极薄膜晶体管可以克服由于Pb原子从PZT层扩散到氧化物导体层中可能引起的各种缺陷，其包括铁电栅极薄膜晶体管的透射特性容易劣化的缺点（ 例如，存储窗口的宽度容易变窄）。