公开(公告)号：US20250046365A1

公开(公告)日：2025-02-06

申请号：US18926916

申请日：2024-10-25

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Daiki Kitagata ,  Shuichiro Yamamoto

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C14/00 ,  H03K3/356

Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.

公开(公告)号：US12165697B2

公开(公告)日：2024-12-10

申请号：US17536493

申请日：2021-11-29

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Daiki Kitagata ,  Shuichiro Yamamoto

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C14/00 ,  H03K3/356

Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.

公开(公告)号：US20220084583A1

公开(公告)日：2022-03-17

申请号：US17536493

申请日：2021-11-29

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Satoshi Sugahara ,  Daiki Kitagata ,  Shuichiro Yamamoto

IPC: G11C11/412 ,  H03K3/356 ,  G11C11/419 ,  G11C11/418

Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.