公开(公告)号：US20110305081A1

公开(公告)日：2011-12-15

申请号：US13053343

申请日：2011-03-22

Applicant: Ji-Sang LEE

Inventor： Ji-Sang LEE

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A method of programming a nonvolatile memory device comprises programming target memory cells among a plurality of memory cells connected to a wordline, performing a first sensing operation on the plurality of memory cells, and selectively performing a second sensing operation on the target memory cells based on a result of the first sensing operation.

Abstract translation: 一种对非易失性存储器件进行编程的方法包括在连接到字线的多个存储器单元中编程目标存储器单元，对所述多个存储器单元执行第一感测操作，并且基于所述目标存储器单元选择性地对所述目标存储器单元执行第二感测操作 这是第一感测操作的结果。

公开(公告)号：US20160011779A1

公开(公告)日：2016-01-14

申请号：US14743267

申请日：2015-06-18

Applicant: Ji-Sang LEE

Inventor： Ji-Sang LEE

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G11C7/106 ,  G11C7/1087 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C2207/2245

Abstract: An operating method of a nonvolatile memory device is provided which includes receiving a command and an address for a program operation of a first plane, and first data to be programmed at the first plane. A multi-plane dumping command is received after the first data is received, and a command and an address for a program operation of a second plane are received. Second data to be programmed at the second plane is received while a multi-plane dumping operation of the first data is conducted on the first plane.

Abstract translation: 提供了一种非易失性存储装置的操作方法，包括接收第一平面的编程操作的命令和地址以及要在第一平面编程的第一数据。 在接收到第一数据之后接收多平面转储命令，并且接收用于第二平面的程序操作的命令和地址。 当在第一平面上进行第一数据的多平面倾倒操作时，接收在第二平面处要编程的第二数据。

公开(公告)号：US20140010021A1

公开(公告)日：2014-01-09

申请号：US14023787

申请日：2013-09-11

Applicant: Ji-Sang LEE ,  Kihwan CHOI

Inventor： Ji-Sang LEE ,  Kihwan CHOI

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

Abstract: In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled.

Abstract translation: 在一个实施例中，该方法包括接收读取存储在与第一字线相关联的第一存储器单元中的数据的请求，以及响应于该请求对与第二字线相关联的至少一个存储器单元执行第一读取操作。 第二字线在字线编程顺序中跟随第一字线，并且在第一时间段执行第一读取操作。 该方法还包括基于来自第一读取操作的输出对第一存储器单元执行第二读取操作。 如果从执行第一读取操作的输出指示第一存储器单元没有耦合，则第二次读取操作执行第二时间段，并且第一时间段比第二时间段短。

公开(公告)号：US20110179322A1

公开(公告)日：2011-07-21

申请号：US12975476

申请日：2010-12-22

Applicant: Ji-Sang LEE ,  Oh-Suk KWON

Inventor： Ji-Sang LEE ,  Oh-Suk KWON

IPC: G06F11/267 ,  G11C16/04 ,  G11C16/34 ,  G11C29/42

CPC classification number: G11C16/3459 ,  G06F11/1048 ,  G11C16/3454 ,  G11C2029/0411

Abstract: A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.

Abstract translation: 程序验证电路包括故障状态计数单元和故障比特计数单元。 故障状态计数单元计数多个程序状态中的程序状态失败，并且产生指示是否需要对故障位进行计数的第一程序模式信号。 故障位计数单元响应于第一编程模式信号有选择地计数故障位，并产生指示程序操作是否完成的第二程序模式信号。

公开(公告)号：US20100232228A1

公开(公告)日：2010-09-16

申请号：US12715692

申请日：2010-03-02

Applicant: Hong Soo JEON ,  Ji-Sang LEE ,  Oh Suk KWON

Inventor： Hong Soo JEON ,  Ji-Sang LEE ,  Oh Suk KWON

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3454

Abstract: A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing the distribution voltage and the second verify voltage.

Abstract translation: 一种对存储器件进行编程的方法包括比较第一验证电压和至少一个存储器单元的分配电压，并且如果比较结果是通过，则调整分配电压直到分配电压高于第二验证电压 同时比较分配电压和第二验证电压。