SELF BIASED RECTIFIER CIRCUIT AND WIRELESS POWER RECEIVER COMPRISING THE SELF BIASED RECTIFIER CIRCUIT

    公开(公告)号:WO2020070649A1

    公开(公告)日:2020-04-09

    申请号:PCT/IB2019/058351

    申请日:2019-10-01

    Abstract: A self-biased rectifier circuit (300A) includes first (AC1) and second (AC2) input terminals and first (VDD) and second (VSS) output terminals. The self-biased rectifier circuit also includes a rectifier having first (M1), second (M2), third (M3), and fourth (M4) transistors, each having a source, gate, and drain. The sources of the first and second transistors and the gates of the third and fourth transistors are coupled to the first input terminal. The sources of the third and fourth transistors and the gates of the first and second transistors are coupled to the second input terminal. The drains of the first and third transistors are coupled to the second output terminal. The drains of the second and fourth transistors are coupled to the first output terminal. A feedback circuit (FB1, FB2) includes a plurality of transistors configured as at least one rectifier. The feedback circuit is coupled to the gates of the first and third transistors and the plurality of transistors are configured to provide a first biasing voltage or a second biasing voltage to the gates of the first and third transistors depending upon a magnitude of power or voltage applied to the first and second input terminals. Additionally, or alternatively, the feedback circuit is coupled to the gates of the second and fourth transistors and the plurality of transistors are configured to provide a first biasing voltage or a second biasing voltage to the gates of the second and fourth transistors depending upon a magnitude of power or voltage applied to the first and second input terminals.

    CONTROLLING DEVICES USING FACIAL MOVEMENTS
    3.
    发明申请

    公开(公告)号:WO2021024138A1

    公开(公告)日:2021-02-11

    申请号:PCT/IB2020/057279

    申请日:2020-07-31

    Abstract: A system for controlling at least one device includes a pair of glasses having a glasses frame. A plurality of magnetic sensors, a processor coupled to the plurality of magnetic sensors, and a wireless communication transmitter coupled to the processor are arranged on or in the glasses frame. A plurality of magnetic skins tags are arranged on a human face. The plurality of magnetic sensors sense movement of at least one of the plurality of magnetic skin tags and transmit a signal corresponding to the sensed movement to the processor. The processor, responsive to receipt of the signal corresponding to the sensed movement, transmits a signal for controlling the at least one device via the wireless communication transmitter to a processor of a power-driven mobility device.

    MECHANICAL FREQUENCY UPCONVERTER
    6.
    发明申请

    公开(公告)号:WO2019197950A1

    公开(公告)日:2019-10-17

    申请号:PCT/IB2019/052771

    申请日:2019-04-04

    Abstract: A mechanical frequency upconverter includes a body having a cavity. A low-frequency membrane is coupled to the body and arranged adjacent to the cavity. The low-frequency membrane is a permanent magnet or a permanent magnet is affixed to the low-frequency membrane. A high-frequency membrane is coupled to the body and arranged adjacent to the cavity. The high-frequency membrane includes a magnetic metal. Oscillation of the low-frequency membrane at a first frequency causes the high-frequency membrane to oscillate at a second frequency, which is higher than the first frequency.

    STRONGARM LATCH COMPARATOR AND METHOD
    7.
    发明申请

    公开(公告)号:WO2018203149A1

    公开(公告)日:2018-11-08

    申请号:PCT/IB2018/050290

    申请日:2018-01-17

    Abstract: A StrongARM latch comparator (500) includes first and second p-type metal- oxide-semiconductor, PMOS, cross-coupled transistors (T1, T2); third and fourth n- type metal-oxide-semiconductor, NMOS, cross-coupled transistors (T3, T4), wherein the first PMOS cross-coupled transistor (T1) has a gate electrically coupled to a gate of the third NMOS cross-coupled transistor (T3) and the second PMOS cross- coupled transistor (T2) has a gate electrically coupled to a gate of the fourth NMOS cross-coupled transistor (T4); and fifth and sixth input transistors (T5, T6). The fifth input transistor (T5) is electrically connected between the first PMOS cross-coupled transistor (T1) and the third NMOS cross-coupled transistor (T3), and the sixth input transistor (T6) is electrically connected between the second PMOS cross-coupled transistor (T2) and the fourth NMOS cross-coupled transistor (T4).

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