公开(公告)号：JPH10135483A

公开(公告)日：1998-05-22

申请号：JP26237997

申请日：1997-09-26

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU KYOKAN ,  RI SEISAI ,  SHIN MINTETSU

IPC: H01L29/06 ,  H01L21/335 ,  H01L29/66 ,  H01L29/772 ,  H01L29/80

Abstract: PROBLEM TO BE SOLVED: To realize multifunction, high-operation frequency and low-consumption power by bending the path of electrons between a source electrode and a drain electrode of a multifunctional quantum diffraction utilizing a two-dimensional electron gas quantum well structure. SOLUTION: A quantum diffraction transistor has such a constitution that an electron path between a source electrode 9B and a drain electrode 10B of a multifunctional quantum transistor using a quantum well structure of two dimensional electron gas formed in a semiconductor different type junction part such as an AlGaAs/GaAs layer is bent and the reflective diffraction grating 15 (one or a plurality) is inserted into the bent part. Thereby, advantages such as a multifunctional property with a large number of ON/OFF functions, high operation frequencies, low power consumption, further lower gate critical operation voltage, further higher transconductance and negative transconductance can be realized.

公开(公告)号：JPH10173185A

公开(公告)日：1998-06-26

申请号：JP24477397

申请日：1997-08-26

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU KYOKAN ,  RI SEISAI ,  SHIN MINTETSU

IPC: H01L29/78 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To make the saturated drain voltage of a FET larger than the one of a conventional FET under the condition of an arbitrary gate voltage, by manufacturing the FET with a non-conductor layer whose thickness of its source and drain sides are different from each other. SOLUTION: Laminating a non-conductor layer 2 and a gate 3 on a semiconductor substrate 1, a source 4 and a drain 5 are formed in its surface portions present in both side portions of the gate 3. In this case, the thickness of the non-conductor layer portion 2 present on the source side 4 is made so larger than the one present on the drain side 5 that when operating a FET the thickness of a channel layer 6 formed in its surface portion present under the gate 3 and present on the drain side 5 is made larger than the one present under the gate 3 and present on the source side 4. Further, a depletion layer 7 present under the source 4, the drain 5, and the channel layer 6 is also formed to have the same configuration as the layer 6. Thereby, the quantity of the saturated drain current of the FET can be increased to make the linear current-voltage characteristic of the FET improvable.