公开(公告)号：JPH09181713A

公开(公告)日：1997-07-11

申请号：JP31611296

申请日：1996-11-27

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： HIIYON JIYUN ,  BUMUCHIEORU RII ,  KUUONCHIYURU PAAKU

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04

Abstract: PROBLEM TO BE SOLVED: To apply re-timing to data stably even when a static skew due to a difference of delay between a re-timing clock pulse and data bits and a dynamic skew due to a change in time and temperature are in existence in binary data bits sent at a high speed. SOLUTION: The device is provided with a means 201 generating nsets of multiple phase clock pulses with n-phases from an external input clock pulse, a means 202 providing an output of a control signal to select one clock pulse or over whose transition takes place close to the middle of an interval of data bits received externally among the n-sets of multiple phase clock pulses, a means '203 receiving the multiple phase clock pulses and a retiming clock pulse selection signal so as to synthesize the retiming clock pulses in a way that the transition of the re-timing clock pulse takes place in the middle of the interval of the data bits received externally, and a means 204 applying re-timing to externally received data by using the synthesized re-timing clock pulse.