公开(公告)号：KR20100041981A

公开(公告)日：2010-04-23

申请号：KR20080101061

申请日：2008-10-15

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BYUN SANG JIN ,  SHIM JAE HOON ,  YU HYUN KYU

IPC: H04L27/22 ,  H04L27/18

CPC classification number: H04L27/233 ,  H04L27/2338

Abstract: PURPOSE: A PSK demodulator using a time to digital converter is provided to remove a synchronous circuit for synchronizing a PSK signal and a clock signal by performing sampling according to asynchronous clock signal in a PSK signal. CONSTITUTION: A phase deviation demodulator comprises a band pass filter(10), an amplitude restriction(20), a poly-phase clock generating part(30), and a time to digital converter(40). The band pass filter filters the PSK signal inputted into a phase deviation demodulator and passes through only a recognizable signal band. The amplitude restriction restricts the amplitude of the PSK signal filtered through the band pass filter. The poly-phase clock generating part generates M clock signal having M phases. The poly-phase clock generating part controls the resolution of the time to digital converter by controlling the frequency and phase number of the clock signal.

Abstract translation: 目的：提供使用时间 - 数字转换器的PSK解调器，以通过根据PSK信号中的异步时钟信号执行采样来去除用于同步PSK信号和时钟信号的同步电路。 构成：相位差解调器包括带通滤波器（10），振幅限制（20），多相时钟产生部分（30）和时 - 数转换器（40）。 带通滤波器对输入到相位差解调器中的PSK信号进行滤波，仅通过可识别的信号频带。 幅度限制限制通过带通滤波器滤波的PSK信号的幅度。 多相时钟生成部生成具有M相的M时钟信号。 多相时钟发生部通过控制时钟信号的频率和相位数来控制时间到数字转换器的分辨率。