公开(公告)号：JPH09198879A

公开(公告)日：1997-07-31

申请号：JP34432196

申请日：1996-12-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： IEONHO PAAKU ,  JIYONAAMU JIYUN

IPC: G06F12/08 ,  G11C15/04 ,  H04L12/70 ,  H04L12/701 ,  H04L12/741

Abstract: PROBLEM TO BE SOLVED: To make it possible to rapidly address convert without limit of the accessing time and without delay at the time of accessing by providing a null controller, lookup table, reception back selector and transmission back selector. SOLUTION: The registered data to be transmitted from a CPU controller 11 is divided at the time of registering, and these data are stored at the moment that a write address signal and a write control signal simultaneously become '1'. When the data are received via a transmission line, a reception lookup table compares the received data with the storage data of each row of the latch circuit group, outputs a comparison result of '0' value only from a matching detector of the rows where all the bits coincide, and the detector outputs the value of the corresponding address of tx match [n] as along as the comparison result of the '0' value and empty of '1' value are input. The other transmission lookup table similarly operates to the reception lookup table.