公开(公告)号：GB2484579A

公开(公告)日：2012-04-18

申请号：GB201117328

申请日：2011-10-07

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM HYUK ,  JEON IN SAN ,  KIM SEONG MIN ,  KOO BON TAE

IPC: H04L1/18

Abstract: In a chase combining (CC) hybrid automatic repeat request (HARQ) system in which previously-transmitted packet information 304 is combined with retransmitted packets, a log-likelihood ration (LLR) is computed for both a parity bit (607) and a systematic bit (606) and supplied 308 to a combiner 303 to be combined with data used for channel decoding 307. Decoding may be iterative (eg. LDPC or turbo) and use BCH, Reed-Solomon, SOVA or MAP algorithms.

公开(公告)号：GB2484579B

公开(公告)日：2012-12-12

申请号：GB201117328

申请日：2011-10-07

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM HYUK ,  JEON IN SAN ,  KIM SEONG MIN ,  KOO BON TAE

IPC: H04L1/18

Abstract: A packet combining device for a communication system using hybrid automatic repeat request (HARQ) includes: a HARQ buffer; a combiner configured to combine data which is previously received and stored in the HARQ buffer with newly-received data; and a channel decoder configured to attempt channel decoding by using the combined received data provided from the combiner and provide one or more of log likelihood ratios (LLRs) computed for a systematic bit and a parity bit of the combined received data to the combiner such that the one or more LLRs are combined with the data used for channel decoding.

公开(公告)号：KR20120071245A

公开(公告)日：2012-07-02

申请号：KR20100132911

申请日：2010-12-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JEON IN SAN ,  KIM HYUK ,  KIM SEONG MIN

IPC: H03M13/27

CPC classification number: H03M13/276 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/6502 ,  H03M13/6525

Abstract: PURPOSE: An interleaving address generator is provided to easily generate forward and reverse direction addresses by changing an initial stored value. CONSTITUTION: An interleaving address generator includes a multiplier(201) which multiples a preset coefficient and a constant and a plurality of address generation blocks(210-240) in which the outputs of the multiplier are calculated and generates an interleaving address. The plurality of address generation blocks is parallely connected to the multiplier by line. Each of the plurality of address generation blocks includes first adders(211,221,231,241) adding the outputs of first registers(212,222,232,242) to the outputs of the multiplier and a first register storing the outputs of the first adders. Each of the plurality of address generation blocks includes second adders(213,223,233,243) and second registers(214,224,234,244) storing the outputs of the second adders.

Abstract translation: 目的：提供交织地址发生器，通过改变初始存储值来容易地生成正向和反向地址。 构成：交织地址生成器包括倍增预置系数和常数的乘法器（201）和多个地址生成块（210-240），其中计算乘法器的输出并产生交织地址。 多个地址生成块与乘法器并行地并行连接。 多个地址生成块中的每一个包括将第一寄存器（212,222,232,242）的输出与乘法器的输出相加的第一加法器（211,221,231,241）和存储第一加法器的输出的第一寄存器。 多个地址生成块中的每一个包括存储第二加法器的输出的第二加法器（213,223,233,243）和第二寄存器（214,224,234,244）。