公开(公告)号：FR2728747B1

公开(公告)日：1999-05-21

申请号：FR9509713

申请日：1995-08-10

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： LEE SANG HOON ,  KO JUNG HOON ,  KIM JONG HO ,  JEON KYUNG KYU

IPC: H04L12/00 ,  H04J3/08 ,  H04Q11/04 ,  H04J14/08 ,  H04L12/43

Abstract: An add-drop control apparatus includes first and second data input units for inputting external first and second data signals, respectively, a frame phase arrangement unit for arranging phases of an external add data signal, an add data controller for transferring a first add data signal from the frame phase arrangement unit to a host stage in a selected one of a plurality of operating modes under control of a processor, a drop data controller for transferring selectively first and second drop data signals from the first and second data input units and a local loop back data signal from the add data controller to a tributary stage in the selected operating mode under the control of the processor, first and second data output controllers for transferring selectively first and second remote loop back data signals from the first and second data input units, first and second through data signals from the second and first data input units and second and third add data signal signals from the add data controller externally in the selected operating mode under the control of the processor, respectively, and an alarm indication signal insertion controller for checking an external add frame synchronous signal and outputting an alarm indication signal control signal to the add data controller in accordance with the checked result.

公开(公告)号：FR2728747A1

公开(公告)日：1996-06-28

申请号：FR9509713

申请日：1995-08-10

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： LEE SANG HOON ,  KO JUNG HOON ,  KIM JONG HO ,  JEON KYUNG KYU

IPC: H04L12/00 ,  H04J3/08 ,  H04Q11/04 ,  H04J14/08 ,  H04L12/43

Abstract: An add-drop control apparatus includes first and second data input units for inputting external first and second data signals, respectively, a frame phase arrangement unit for arranging phases of an external add data signal, an add data controller for transferring a first add data signal from the frame phase arrangement unit to a host stage in a selected one of a plurality of operating modes under control of a processor, a drop data controller for transferring selectively first and second drop data signals from the first and second data input units and a local loop back data signal from the add data controller to a tributary stage in the selected operating mode under the control of the processor, first and second data output controllers for transferring selectively first and second remote loop back data signals from the first and second data input units, first and second through data signals from the second and first data input units and second and third add data signal signals from the add data controller externally in the selected operating mode under the control of the processor, respectively, and an alarm indication signal insertion controller for checking an external add frame synchronous signal and outputting an alarm indication signal control signal to the add data controller in accordance with the checked result.