公开(公告)号：JPH0262072A

公开(公告)日：1990-03-01

申请号：JP7367389

申请日：1989-03-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIMU KUWAN SUU ,  CHIE SAN FUN ,  KIMU IOFUAN ,  KIMU BOU ,  I JINHO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/70 ,  H01L29/732

Abstract: PURPOSE: To increase the degree of integration and operating speed of a composite semiconductor element, by mounting a bipolar element formed by minimizing the width of its inactive base region and a highly integrated CMOS element on one water in a mixing state. CONSTITUTION: After an N -buried layer 104 is formed on the surface 102 of a P -type silicon wafer substrate by diffusion, an N-type epitaxial layer 103 is grown and deposited by doping the layer 104 with phosphorus. Then, after a P -type junction separating area 106 is prescribed by utilizing a field mask, boron is injection into the area 106. After injection, an oxide film 107 is grown and the gates 111 of an NMOS element and a PMOS element and the emitter 112 and collector 113 of a bipolar transistor are fomred by anisotropic etching. Then, the sources/drains 116 of the PMOS and NMOS 117 elements are formed by implanting boron ions. Finally, an inactive base region and junctions are fomred so as to reduce the base serial resistance of the bipolar transistor.