公开(公告)号：JPH08148990A

公开(公告)日：1996-06-07

申请号：JP31048194

申请日：1994-12-14

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN CHINGIYOU ,  KIN ZENEI

IPC: G06F7/50 ,  G06F7/44 ,  G06F7/49 ,  G06F7/501 ,  H03K19/20

Abstract: PURPOSE: To provide the operation device of AND logic, which defines the operation rule of AND for operating AND on multi-nary logics while the AND of binary numbers is contained, by containing an operation adder for obtaining a multi-nary logic value fitted to the input of the binary number and the computing element of binary-nary AND for receiving the output of the operation adder and binary input. CONSTITUTION: The AND logic operator 52 receiving the three inputs of multi- nary logic is configured of two AND logic operators 51 receiving two inputs. Such operation device of multi-nary AND logic contains the operation function of existed binary AND and the operation function of binary-multi-nary AND. For calculating the output of the logic circuit by using the binary-multi-nary AND logic operator, the operation circuit is constituted of only one binary- multi-nay AND logic operator and one operation adder. When the multi-nary AND logic operator is used, the configuration of the circuit and the like for operating the multi-nary logic value can be simplified.

公开(公告)号：JPH08148991A

公开(公告)日：1996-06-07

申请号：JP31048294

申请日：1994-12-14

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN CHINGIYOU ,  KIN ZENEI

IPC: G06F7/50 ,  G06F7/00 ,  G06F7/44 ,  G06F7/501 ,  H03K19/20

Abstract: PURPOSE: To provide the operation device of OR, which defines the operation rule of OR for OR-operating multi-nary logics while the operation of OR of binary numbers is contained, by containing an operation adder for obtaining a multi-nary logic value fitted to the input of the binary number and the binary- multi-nary OR logic operator for receiving the output of the operation adder and binary input. CONSTITUTION: The OR logic operator 52 having the three inputs of multi-nary logic is configured of two multi-nary OR logic operators 51 having two inputs. Such multi-nary OR logic operator contains the operation function of existed binary OR logic operator and the operation function of binary-multi-nary OR logic operator. For calculating the output of a logic circuit by using the operator of binary-multi-nary OR logic, an operation circuit is configured of only one binary-multi-nary OR logic operator and one operation adder. When the multi- nary OR logic operator is used, the configuration of the circuit for operating the multi-nary logic value can be simplified.