公开(公告)号：DE4445565C2

公开(公告)日：2002-10-24

申请号：DE4445565

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： LEE KYU-HONG ,  LEE JIN-HYO

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732

Abstract: Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed upward the first pillar to expose a surface of the first pillar; injecting an impurity in the first pillar to form a base at a center portion thereof; injecting an impurity to form an emitter at an upper portion of the first pillar; depositing a third polysilicon layer on the emitter, the third polysilicon layer being formed wider than the emitter; and forming self-aligned contact holes to form electrodes through the contact holes.

公开(公告)号：GB2296377A

公开(公告)日：1996-06-26

申请号：GB9425735

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： LEE KYU-HONG ,  LEE JIN-HYO

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732

Abstract: Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed upward the first pillar to expose a surface of the first pillar; injecting an impurity in the first pillar to form a base at a center portion thereof; injecting an impurity to form an emitter at an upper portion of the first pillar; depositing a third polysilicon layer on the emitter, the third polysilicon layer being formed wider than the emitter; and forming self-aligned contact holes to form electrodes through the contact holes.

公开(公告)号：DE4445565A1

公开(公告)日：1996-06-27

申请号：DE4445565

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： LEE KYU-HONG ,  LEE JIN-HYO

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732

Abstract: A pillar bipolar transistor which has a bidirectional operation characteristic in which the parasitic junction capacitance of a base electrode is reduced. A method for fabricating the transistor comprises etching a substrate (21) using a first patterned insulating layer (32) as a mask to form first and second pillars (10, 20) separated by a trench injecting an impurity using a mask (33, 32) to form a collector (23) under the first and second pillars and in the second pillar (20); depositing a first oxide layer (34) and a first polysilicon layer (24') polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base (24); etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming buried polysilicon to form the connection portion (25); depositing a second oxide layer (36) and a second polysilicon layer (35) polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed on the top of the first pillar to expose a surface of the first pillar; injecting an impurity in the first pillar to form a base (27) at a centre portion; injecting an impurity to form an emitter (28) at an upper portion of the first pillar; depositing a third polysilicon layer (26) on the emitter, the third polysilicon layer being formed on an area wider than the emitter; and forming self-aligned contact holes to form electrodes (29) through the contact holes.