公开(公告)号：DE4345029A1

公开(公告)日：1994-07-07

申请号：DE4345029

申请日：1993-12-30

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM KI CHUL ,  MIN BYUNG KI

IPC: H03M7/30 ,  G06F17/14 ,  G06F7/548

Abstract: A discrete cosine transform circuit including a shuffle circuit with n (n is an integer) shuffle stages, the n shuffle stages sequentially having 2n, 2n-1, . . . , 21 input/output stages in such a manner that a first one of the n shuffle stages has the 2n input/output stages and a nth one of the n shuffle stages has the 21 input/output stages, the nth shuffle stage including first and second RACs for performing a discrete cosine transform using a distributed arithmetic process, the first RAC having 2n-2 input/output stages, the second RAC having 2n-1 input/output stages. A path switching section is connected to the input stages of the shuffle circuit for changing a transfer path of output information from the output stages of the shuffle circuit according to whether the discrete cosine transform to be processed is a forward discrete cosine transform or an inverse discrete cosine transform. A first selection section is connected to the input stages of the first RAC and a second selection section is connected to the input stages of the second RAC. The first and second selection sections select information according to whether the discrete cosine transform to be processed is the forward discrete cosine transform or the inverse discrete cosine transform and apply the selected information to the first and second RACs, respectively.

公开(公告)号：DE4345029C2

公开(公告)日：1999-10-28

申请号：DE4345029

申请日：1993-12-30

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM KI CHUL ,  MIN BYUNG KI

IPC: H03M7/30 ,  G06F17/14 ,  G06F7/548

Abstract: A discrete cosine transform circuit including a shuffle circuit with n (n is an integer) shuffle stages, the n shuffle stages sequentially having 2n, 2n-1, . . . , 21 input/output stages in such a manner that a first one of the n shuffle stages has the 2n input/output stages and a nth one of the n shuffle stages has the 21 input/output stages, the nth shuffle stage including first and second RACs for performing a discrete cosine transform using a distributed arithmetic process, the first RAC having 2n-2 input/output stages, the second RAC having 2n-1 input/output stages. A path switching section is connected to the input stages of the shuffle circuit for changing a transfer path of output information from the output stages of the shuffle circuit according to whether the discrete cosine transform to be processed is a forward discrete cosine transform or an inverse discrete cosine transform. A first selection section is connected to the input stages of the first RAC and a second selection section is connected to the input stages of the second RAC. The first and second selection sections select information according to whether the discrete cosine transform to be processed is the forward discrete cosine transform or the inverse discrete cosine transform and apply the selected information to the first and second RACs, respectively.