公开(公告)号：JPH07200262A

公开(公告)日：1995-08-04

申请号：JP30086194

申请日：1994-12-05

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI MITSUHIRO ,  CHIYOU SEIRIYUU ,  RI AKINARI

IPC: G06F7/52 ,  G06F7/50 ,  G06F7/535 ,  G06F7/72 ,  G09C1/00 ,  G06F7/38

Abstract: PURPOSE: To provide a method for decreasing the mean number of times of addition execution, and increasing the reduction speed by fixing the number of times of the addition necessary for one time of the execution of a reduction algorithm to the maximum two times. CONSTITUTION: A method for modulo reduction using a preliminary calculation table is provided with a first stage in which a value stored in a table with the number of upper log2 t (t>=1) bits for reduction as an index is retrieved, and added to the number of lower (n) (n>=512) bits, and a second stage in which when overflow (1bit) is generated as the result of the addition of the number retrieved in the table to the number of the lower (n) bits in the first stage, the overflow is removed, and the execution of the arithmetic operation is ended. Moreover, this method is provided with a third state in which when the overflow is not generated in the second stage, N on modulo N is added to the result in the first stage, and the execution of the arithmetic operation is ended.