SELF-ALIGNING GALLIUM ARSENIDE (GAAS) FIELD EFFECT TRANSISTOR MAKING USE OF MULTILAYER RESIST

    公开(公告)号:JPH0282629A

    公开(公告)日:1990-03-23

    申请号:JP31400288

    申请日:1988-12-14

    Abstract: PURPOSE: To form an N layer through a self-aligned method for contact of low resistance by a method wherein a multilayer photoresist prescribed in dimensional and formed through a photograph transfer technique is transferred as reduced to a specific scale through reactive ion etching, and a required gate plated with gold, T-shaped, and high in dimensional accuracy is formed taking advantage of side etching of a lower photoresist layer. CONSTITUTION: A temporary gate 111 is formed by etching through a reduction transfer method wherein a shape of size 0.6 to 1.0μm is transferred at a reduction ration 2:1. Titanium is evaporated on tungsten silicide, plating is carried out making the evaporated titanium serve as an electrode, plating is carried out at a growth rate of 0.1μm/min or so at a temperature of 50 deg.C taking advantage of the exposed titanium 104a as an electrode, whereby a specified T-shaped gate is formed. Taking advantage of a photograph transfer method, the shape of a transistor region which comprises source. drain regions is limited by a photoresist 105b, silicon ions are implanted at an ion dose of 1E13 to 5E13/cm with en energy of 100 to 200keV using the T-shaped gate as a mask, whereby a silicon ion-implanted layer 115 as an N layer is formed at the resistive joint of a source and a drain in a self-aligned manner.

Patent Agency Ranking