公开(公告)号：JPH08161434A

公开(公告)日：1996-06-21

申请号：JP31372494

申请日：1994-12-16

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SHIN SOUKAN

IPC: G06F15/18 ,  G06K9/66 ,  G06N3/00 ,  G06N3/04

Abstract: PURPOSE: To simultaneously separate and recognize a pattern by providing a feature layer for executing different phase oscillations against the mutually different patterns and a character detecting layer for recognizing the phase- synchronized character. CONSTITUTION: A circuit network is attained by the three stages of an input stage 50, a feature extracting stage(FEL) 51 and a character recognizing layer(ADL) 52 as in the case of Jang for separating and recognizing the pattern. Inter-nerve phase connection in the feature extracting layer 51 is decided by the feed-back of the selective oscillation from the character detecting quantity nerve to a lower layer. The selective oscillation of character detecting quantity 52 is decided by the matching of the connection strength pattern from feature extracting quantity to a character detecting layer 52 with an input pattern and by mutual restricting competition. Thus, the oscillation of the nerve in the feature extracting layer 51, which is synchronized by one phase, corresponds to the one specified pattern and the feature extracting nerves corresponding to the patterns concerning the mutually different patterns are oscillated by the mutually different phases.

公开(公告)号：JPH07168901A

公开(公告)日：1995-07-04

申请号：JP20650194

申请日：1994-08-31

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SHIN SOUKAN ,  SHIN SOUKON

IPC: G06F15/18 ,  G06G7/60 ,  G06N3/06 ,  G06N3/063

Abstract: PURPOSE: To provide a neural circuit to be the component of an artificial neural net. CONSTITUTION: The neural circuit is composed of a synapse circuit 10 for discharging or absorbing a current I3 proportional to the weighted voltage Wij when applying a prescribed input signal Sj(t), neural cell circuit 20 for integrating the output current I3 from this circuit 10 with respect to space-time, and axis-cylinder projection circuit 30 for converting the output signal of the neural cell circuit 20 to a prescribed pulse string corresponding to a prescribed reference signal. The synapse circuit 10 is composed of combination of a transistor M1 to which the weighted voltage signal Wij is applied, a transistor M2 to which a prescribed signal Vr3 is applied and a transistor M3, to which the prescribed input signal Sj(t) is applied, linked between two transistors M1 and M2.