公开(公告)号：JP2002133859A

公开(公告)日：2002-05-10

申请号：JP2000403355

申请日：2000-12-28

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： YAN IRUSOKU ,  YU PYONGON ,  YU INGYU ,  I WONZE ,  ZO BYONIKU

IPC: G11C14/00 ,  G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a single transistor ferroelectric memory and a driving method therefor, by which reading/writing is made random. SOLUTION: A word line control part 52 and a source line control line 53 includes a decoder circuit for selecting a specific cell in accordance with an address inputted at the time of reading and writing and are for providing the selected cell with a prescribed voltage, and a reading voltage generating part 51 is for generating lots of reading voltages at the time of reading. A memory cell array is an arrangement of lots of word lines, bit lines, source lines, and ferro-electric transistors, and this memory cell array is provided with lots of well lines which are arranged in parallel to the bit lines and the source lines and form wells common to the columns, and are connected to the source lines of the columns but electrically isolated from the adjacent wells common to the columns.