公开(公告)号：KR20080105399A

公开(公告)日：2008-12-04

申请号：KR20070052932

申请日：2007-05-30

Applicant: KOREA ELECTRONICS TELECOMM ,  KYUNGPOOK NAT UNIV IND ACAD

Inventor： LIM SANG KYU ,  KIM KANG WOOK ,  PARK HYUN ,  KO JE SOO

IPC: H03L7/16

CPC classification number: H03L7/101 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

Abstract: A method and an apparatus for synthesizing a frequency using a D-flip flop are provided to recover a synchronization state at high speed by feeding back an error and correcting the error when the synchronization is released. A frequency synthesizer includes a separating unit(120), an IF signal generator(130,131), and a D-flip flop frequency acquisition unit(140). A separating unit separates an output signal of an oscillator of a phase locked loop into two signals with phase difference of 90 degrees. The IF signal generator generates two IF signals by mixing the reference frequency of the phase-locked loop with two separated signals. The D-flip flop frequency acquisition unit applies two IF signals to the D- flip flop. The D-flip flop frequency acquisition unit controls the oscillator frequency based on the polarity of the phase difference of two applied signals.

Abstract translation: 提供了一种使用D触发器合成频率的方法和装置，以通过反馈错误并在同步被释放时校正错误来高速恢复同步状态。 频率合成器包括分离单元（120），IF信号发生器（130,131）和D触发器频率获取单元（140）。 分离单元将锁相环的振荡器的输出信号分离为相位差为90度的两个信号。 IF信号发生器通过将锁相环的参考频率与两个分离的信号混合来产生两个IF信号。 D触发器频率采集单元向D-触发器施加两个IF信号。 D触发器频率获取单元基于两个施加信号的相位差的极性来控制振荡器频率。