公开(公告)号：JP2001094540A

公开(公告)日：2001-04-06

申请号：JP2000243623

申请日：2000-08-11

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DUNLOP ALFRED EARL ,  FISCHER WILHELM C ,  OTA YUSUKE

IPC: H03L7/099 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To obtain a specific frequency again from a burst mode signal by using one signal device. SOLUTION: A clock can be collected from a burst mode signal having a specific frequency by using one device which is similar to American patents No.5, 237, and 290 except that a delay line used in each oscillator with a gate is selected in a controllable state so that oscillators with gates can provide clock signals having multiple frequencies. The same frequency is normally selected for both oscillators with gates. An oscillator with an internal gate is composed of a delay element. Relative frequencies are determined by the ratio of the number of delay elements in various oscillators with internal gates. When a delay element constituting an oscillator with an internal gate is an inverter, a phase splitter is usable so as to obtain secure oscillation even when the number of delay elements is always odd and two ratios are necessary with restored frequencies.

公开(公告)号：CA2323649A1

公开(公告)日：2001-04-25

申请号：CA2323649

申请日：2000-10-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DUNLOP ALFRED EARL ,  KALAVADE ASAWAREE P

IPC: G06F13/38 ,  H04L29/02

Abstract: A network interface architecture includes a processor having an associated program memory, and a programmable logic device coupled to the processor. A connection port of the logic device is adapted to be coupled to a medium of a selected network having a defined network protocol, and the logic device has an associated configuration memory. A data communication path is coupled to the processor and the logic device, and is arranged to connect with a host device for transferring data between the host device and a network to which the logic device is coupled. The processor responds to information identifying a selected network by loading corresponding network protocol data from the configuration memory and the program memory into the logic device and the processor. The host device may include, without limitation, a personal, lap top, desk top or hand-held computer, a network appliance, file server, printer, vending machine, cell phone or the like.

公开(公告)号：CA2323649C

公开(公告)日：2006-11-28

申请号：CA2323649

申请日：2000-10-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KALAVADE ASAWAREE P ,  DUNLOP ALFRED EARL

IPC: H04L29/02 ,  G06F13/38

Abstract: A network interface architecture includes a processor having an associated program memory, and a programmable logic device coupled to the processor. A connection port of the logic device is adapted to be coupled to a medium of a selected network having a defined network protocol, and the logic device has an associated configuration memory. data communication path is coupled to the processor and the logic device, and is arranged to connect with a host device for transferring data between the host device and a network to which the logic device is coupled. The processor responds to information identifying a selected network by loading corresponding network protocol data from the configuration memory and the program memory into the logic device and the processor. The host device may include, without limitation, a personal, lap top, desk top or handheld computer, a network appliance, file server, printer, vending machine, cell phone or the like.