公开(公告)号：JP2001216058A

公开(公告)日：2001-08-10

申请号：JP2000396661

申请日：2000-12-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LEE HYUN ,  RAI Q FAMU ,  DAVID WAYNE POTTER

IPC: G06F3/00 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To provide a method for transferring data through a bus between a transmitting device and a receiving device, capable of increasing bus band width by removing a null cycle. SOLUTION: This is a method and device for dynamically holding a valid data logic level on a bus by using storage capacity specific to the bus. A bus speed is increased by removing the use of any active bus keeper or null cycle. Instead, a two-phase clock is used, and a bus driver drives data on the bus in the first phase of the clock, and the bus driver is turned off at the beginning of the second phase of the clock. A receiving device latches the data in the second phase of the bus clock. Therefore, it is not necessary to provide any null cycle or bus keeper circuit, and it is possible to prevent any bus contention between continuous drivers or any floating node state.

公开(公告)号：JP2001216253A

公开(公告)日：2001-08-10

申请号：JP2000399812

申请日：2000-12-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LEE HYUN ,  DAVID WAYNE POTTER

IPC: G06F13/362 ,  G06F13/364

Abstract: PROBLEM TO BE SOLVED: To provide a data processing method through bus. SOLUTION: This method for processing data through a bus connected to a plurality of devices is composed of (A) a step for receiving a request including the identification information of a destination device for requesting access from a source device to the bus during the cycle of a bus clock, (B) a step for transmitting a first control signal for instructing the source device to input data in response to the request at the input point of a buffer connected between the source device and the bus in response to the request and (C) a step for transmitting a second control signal for prompting the buffer to output the data onto the bus in a bus clock cycle after the transmission of the first control signal. The second control signal is transmitted in the bus clock cycle preceding the tip edge of a clock corresponding to the intended destination device by one cycle of the bus clock or less, and the data occupy the bus only during one bus clock cycle.

公开(公告)号：JP2001110187A

公开(公告)日：2001-04-20

申请号：JP2000279224

申请日：2000-09-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MICHAEL JAMES HANTER ,  LEE HYUN

IPC: G11C11/413 ,  G11C7/06 ,  G11C7/22 ,  G11C11/41 ,  G11C11/419

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device minimizing voltage swing of a bit line and between bit lines of a SRAM and minimizing its spare charge and a reading time. SOLUTION: Relating to this device, a reinforced sense amplifier is provided to the last column of a storage device array. The reinforced sense amplifier detects that differential voltage between bit lines exceeds the minimum detectable threshold value of the reinforced sense amplifier. When differential voltage between bit lines exceeds the minimum detectable threshold of the reinforced sense amplifier, the reinforced sense amplifier makes a feedback signal to a reading control circuit valid, thereby, when differential voltage between bit lines reaches the minimum differential voltage being detectable by the sense amplifier, reading operation is immediately stopped substantially.