DEVICE AND METHOD FOR REDUCING GROUND VOLTAGE

    公开(公告)号:JPH1141092A

    公开(公告)日:1999-02-12

    申请号:JP12199198

    申请日:1998-05-01

    Abstract: PROBLEM TO BE SOLVED: To reduce power line noise by lowering the voltage between a ground point and a neutral reference point by positioning the neutral reference point at a distance from the ground point and exciting the ground point according to the neutral reference voltage at the neutral reference point. SOLUTION: An input terminal 806 is a very-high-impedance terminal, so substantially no current flows between the input terminal 806 and ground point 610 and the voltage at the input terminal 806 becomes substantially equal to the voltage at the ground point 610. Consequently, voltage drop effect caused by an induction element 822 is substantially removed. A buffer amplifier 802 responds the signal of the frequency band of a power line signal transmitter receiver and when the voltages at input terminals 804 and 806 are different, an output terminal excites the ground point 610 through the induction element 820. The output voltage range of the buffer amplifier 802 is normally larger than the voltage difference appearing between the ground point 610 and neutral reference point 328, so the buffer amplifier 802 excites the voltage at the ground point 610 and equalizes it to the voltage at the neutral reference point 328.

    SEGMENTED CORRELATOR ARCHITECTURE FOR DETECTING SIGNAL IN FADING CHANNEL

    公开(公告)号:JP2002190773A

    公开(公告)日:2002-07-05

    申请号:JP2001284225

    申请日:2001-09-19

    Abstract: PROBLEM TO BE SOLVED: To solve problems that a signal supplied to a shift register when a mobile station is moving at a high speed is quickly faded, phase distortion is introduced, the correlation of input signals or input sequences is lost, a low correlator output is generated when the input sequence is correlated with an expected sequence, the low correlator output does not exceed a detection threshold, and the received sequence cannot be detected. SOLUTION: A signal having a known sequence in a high speed fading environment is detected by using segmented correlator architecture. The input sequence of a sample or data is segmented to blocks correlated with individual segments of the known or expected sequence. The sum of correlator outputs is formed by adding the outputs of individual correlators. The absolute value of the sum is compared with a threshold to determine the detection time of the know input sequence. When the input sequence is segmented and the obtained segments are individually correlated with each other, action causing the loss of correlation of signals is reduced in the whole sequence.

    SEGMENTED ARCHITECTURE FOR DETECTION AND DISCRIMINATION OF PLURALITY OF SEQUENCES IN FADING CHANNEL

    公开(公告)号:JP2002111540A

    公开(公告)日:2002-04-12

    申请号:JP2001284240

    申请日:2001-09-19

    Abstract: PROBLEM TO BE SOLVED: To solve the problem where when a mobile station is moving at high speed, a signal supplied to a shift register is subjected to fading at a high speed, where a sequence received by the shift register is damaged partially so as to generate a low fast-Hadamard transform(FHT) output, and where the FHT output to be compared with a threshold does not exceed the threshold and that a received signature sequence cannot be detected or discriminated. SOLUTION: A segmented correlator and an FHT architecture are used, and a known sequence is detected and discriminated in a high-speed fading environment. A sample or data input sequence is segmented into a block. Respective blocks are detected individually by using a correlator/FHT segment. Each sequence, which discriminates the output of each correlator/FHT segment, is added to the corresponding output of another correlator/FHT segment. Each sum is compared with the threshold, and whether a specific sequence is detected and discriminated is determined.

    ACTIVE GROUND COMPENSATION
    4.
    发明专利

    公开(公告)号:CA2232703C

    公开(公告)日:2001-11-27

    申请号:CA2232703

    申请日:1998-03-19

    Abstract: A ground voltage reduction device is connected between a neutral reference node and a ground node defined by two bypass capacitors of a blocking circui t. The ground voltage reduction device senses the voltage difference between the ne utral reference node and the ground node and drives the ground node to reduce the voltage difference between a voltage of the ground node and a voltage of the neutral reference node

    ACTIVE GROUND COMPENSATION
    5.
    发明专利

    公开(公告)号:CA2232703A1

    公开(公告)日:1998-11-08

    申请号:CA2232703

    申请日:1998-03-19

    Abstract: A ground voltage reduction device is connected between a neutral reference node and a ground node defined by two bypass capacitors of a blocking circuit. T he ground voltage reduction device senses the voltage difference between the neutra l reference node and the ground node and drives the ground node to reduce the volt age difference between a voltage of the ground node and a voltage of the neutral ref erence node

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