公开(公告)号：CA2348306A1

公开(公告)日：2002-01-25

申请号：CA2348306

申请日：2001-05-23

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FARYAR ALIREZA FARID ,  SEN MOUSHUMI ,  YAN AN ,  YANG KYEONG HO

IPC: G06T1/20 ,  G06F15/78 ,  H04N7/015 ,  H04N7/26 ,  G06F9/38

Abstract: An efficient hardware architecture and processing method permit pipelined processing stages to be shared in processing samples from a plurality of independent input sequences that are grouped prior to application to the processing arrangement. A high degree of processing engine efficiency and/or reduced delay for accepting new input samples are achieved by applying the signal sequence, {Y j: j=0,1,2,...,MN 1}, obtained by interleaving M signal sequences {Xij: j=0,1,2,...,N-1}, i=1,2,...M}. Thus, processing of sample Yj can start as soon as processing o f sample Yj-M is finished. Accordingly, effective pipeline stage delay, Dp, can be reduced by a factor of M (from D max to D max /M) and the number of required engines (or, equivalently, required time) can be reduced by the same factor M.