公开(公告)号：EP4322017A1

公开(公告)日：2024-02-14

申请号：EP22799223.7

申请日：2022-05-04

Applicant: Lemon Inc.

Inventor： CHEN, Yimin ,  LU, Shan ,  ZHANG, Chuang ,  ZHANG, Junmou ,  CHENG, Yuanlin ,  WANG, Jian

IPC: G06F15/173 ,  G06F13/36 ,  G06F13/38

Abstract: Disclosed are an on-chip integrated circuit, and a data processing apparatus and method. The on-chip integrated circuit comprises: a processor circuit and an accelerator circuit. The processor circuit comprises a processor and a data storage area, the processor being connected to the data storage area by means of a first bus arranged in the processor circuit. The accelerator circuit comprises an accelerator and a second bus, the accelerator being connected to the second bus, the second bus being bridged with the first bus corresponding to the data storage area so as to enable the accelerator to perform data interaction with the data storage area.

公开(公告)号：EP4462263A1

公开(公告)日：2024-11-13

申请号：EP24174215.4

申请日：2024-05-03

Applicant: Beijing Youzhuju Network Technology Co., Ltd. ,  Lemon Inc.

Inventor： XU, Zhilin ,  BAI, Longfei ,  CHEN, Qi ,  CHEN, Yimin ,  LU, Shan ,  WANG, Jian

IPC: G06F12/02 ,  G06N3/045 ,  G06N3/063

Abstract: A data conversion method and apparatus (200/300), an electronic device (400) and a storage medium (600) for converting dimensions of a first data combination, the first data combination includes at least one batch, dimensions of data to which each of the at least one batch corresponds includes a first dimension, a second dimension, and a third dimension. The data conversion method includes: reading n elements in the first data combination according to a first-dimension direction to obtain a first processing group, a first element to an n-th element in the first processing group are arranged according to the first-dimension direction, and n is a positive integer; performing a transpose on the first dimension and the third dimension of the first processing group to obtain a second processing group, a first element to an n-th element in the second processing group are arranged in a third-dimension direction; and writing the first element to the n-th element in the second processing group to a first storage.

公开(公告)号：EP4379546A1

公开(公告)日：2024-06-05

申请号：EP23171150.8

申请日：2023-05-02

Applicant: Lemon Inc. ,  Beijing Zitiao Network Technology Co., Ltd.

Inventor： KUMAR, Satish ,  WANG, Jian

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/52120130101

Abstract: In order to more efficiently use a timing wheel data structure, the timing wheel is halted when there are no tasks in the timing wheel data structure. A current task count across all timing wheel indexes may be stored so that the halting only occurs when the current task count is zero. Instead of a global lock on the timing wheel data structure, task scheduling contexts may be allowed to run concurrently within different indexes while scheduling contexts are forced to run in series within each index. Each index of the timing wheel may comprise a ring buffer. A method of operation may comprise identifying tasks which are missed by a scheduling context; adding identified tasks to a separate data structure; checking the separate data structure for pending tasks; and prioritising scheduling tasks from the separate data structure.

公开(公告)号：EP4321848A1

公开(公告)日：2024-02-14

申请号：EP22799220.3

申请日：2022-05-04

Applicant: Lemon Inc.

Inventor： ZHANG, Chuang ,  LU, Shan ,  ZHANG, Junmou ,  CHEN, Yimin ,  WANG, Jian ,  CHENG, Yuanlin

IPC: G01K7/16

Abstract: Embodiments of the disclosure disclose a circuit and a method for temperature measurement. The circuit includes: a first temperature sensing circuit, a second temperature sensing circuit, and a data processing unit. The first temperature sensing circuit is configured to generate a first measurement signal for representing temperature according to a first current signal input, and a magnitude of the first current signal is correlated to temperature. The second temperature sensing circuit is configured to generate a second measurement signal for representing temperature according to a second current signal input, and the second current signal is independent of temperature. The data processing unit is configured to determine a present temperature according to a first characteristic parameter corresponding to the first measurement signal and a second characteristic parameter corresponding to the second measurement signal. In this way, linearity of the circuit for temperature measurement when measuring the temperature can be improved, and accuracy of a temperature measurement result can be improved.

公开(公告)号：EP4462258A1

公开(公告)日：2024-11-13

申请号：EP24175003.3

申请日：2024-05-09

Applicant: BEIJING YOUZHUJU NETWORK TECHNOLOGY CO. LTD. ,  Lemon Inc.

Inventor： DENG, Pengjie ,  CHEN, Qi ,  CHEN, Yimin ,  LU, Shan ,  WANG, Jian

IPC: G06F11/07 ,  G06F11/30 ,  G06F11/34

Abstract: A bus anomaly detecting method, processing method, apparatus, system, device, and medium. The bus anomaly detecting method includes: at an interface for connecting a bus, activating a detection state in response to an access initiating apparatus sending an access request to an access receiving apparatus so as to, in the detection state, perform anomaly detection on response signal fed back by the access receiving apparatus for each access request, and block an interruption signal sent by the access initiating apparatus (S210); in response to a response signal corresponding to an access request having an anomaly, terminating the detection state, recording bus anomaly information, and sending an interruption signal (S220); and in a case where the response signal corresponding to each access request sent by the access initiating apparatus is received and has no anomaly, terminating the detection state to stop blocking the interruption signal sent by the access initiating apparatus (S230). This bus anomaly detection method can at least detect abnormal response signals in time and handle the abnormal response signals.

公开(公告)号：EP4425353A2

公开(公告)日：2024-09-04

申请号：EP22901924.5

申请日：2022-11-04

Applicant: Lemon Inc.

Inventor： ZHU, Yibo ,  CHEN, Yangrui ,  HE, Jun ,  PENG, Yanghua ,  GUO, Chuanxiong ,  WANG, Jian

IPC: G06F18/214 ,  G06N3/08 ,  G06N3/04 ,  G06F18/25

Abstract: The disclosure relates to a method, apparatus, system, medium and electronic device for graph neural network generation. The method includes: obtaining a subgraph structure, the subgraph structure being configured to reflect a graph structure of a corresponding subgraph, and the subgraph comprising a plurality of nodes and edges between the plurality of nodes; obtaining, based on the subgraph structure and according to a predetermined priority, node features of the plurality of nodes and edge features of the edges from a plurality of memories; the predetermined priority being obtained by sorting the plurality of memories in accordance with memory size in an ascending order; fusing, based on the subgraph structure, the node features of the plurality of nodes and the edge features of the edges to obtain subgraph data; and training, based on the subgraph data, the graph neural network. The method for graph neural network generation of the present disclosure may improve the efficiency of graph neural network training.

公开(公告)号：EP4336193A2

公开(公告)日：2024-03-13

申请号：EP22833767.1

申请日：2022-05-25

Applicant: Lemon Inc.

Inventor： ZHANG, Junmou ,  ZHANG, Dongrong ,  LU, Shan ,  WANG, Jian

IPC: G01R29/02 ,  H03K5/13 ,  G04F10/04

Abstract: Provided are a pulse signal width measurement apparatus and method, a system, and a medium. The apparatus comprises: a buffer link comprising N first buffers, N first AND gates in which one input end is connected to a pulse signal and another input end is connected to the output of a corresponding first buffer, and corresponding N triggers coupled to the output end of each first AND gate, the N first buffers being connected end to end; a path time delay adjustment circuit, wherein the input end of the path time delay adjustment circuit receives the pulse signal and the output end of the path time delay adjustment circuit is connected to the input end of a first buffer; a control apparatus, wherein during each adjustment, the delay generated by the path time delay adjustment circuit is controlled, according to a preset adjustment step length, to be reduced from a preset time delay by at least one preset adjustment step length until the output of the Pth trigger changes; and a measurement apparatus, wherein the width of the pulse signal is measured at least according to the result output by the output end of each trigger, the delay of each first buffer, and the delay of the path time delay adjustment circuit.

公开(公告)号：EP4321878A1

公开(公告)日：2024-02-14

申请号：EP22799221.1

申请日：2022-05-04

Applicant: Lemon Inc.

Inventor： ZHANG, Junmou ,  LU, Shan ,  ZHANG, Chuang ,  CHEN, Yimin ,  WANG, Jian ,  CHENG, Yuanlin

IPC: G01R19/00

Abstract: Disclosed are an integrated circuit internal voltage detection circuit, a detection method, and an integrated circuit. The circuit comprises: a first current source, a first branch and a second branch, the first branch and the second branch being used for dividing a current signal output by the first current source. The first branch comprises a first voltage control current element and a first load connected in series, and the second branch comprises a current signal detection element and a second load connected in series. A control signal input end of the first voltage control current element inputs a voltage signal to be detected. The current signal detection element is used for outputting in real time a preset signal representing a second current flowing through the second branch, so that a change of the voltage signal to be detected is determined on the basis of the preset signal.

公开(公告)号：EP4495785A1

公开(公告)日：2025-01-22

申请号：EP24184940.5

申请日：2024-06-27

Applicant: BEIJING YOUZHUJU NETWORK TECHNOLOGY CO. LTD. ,  Lemon Inc.

Inventor： XU, Zhilin ,  CHEN, Qi ,  BAI, Longfei ,  CHEN, Yimin ,  WANG, Jian

IPC: G06F12/04 ,  G06F5/01 ,  G06F7/06 ,  G06F7/26

Abstract: The present disclosure provides a data processing method and apparatus, an electronic device, and a storage medium. The data processing provided by the present disclosure includes: receiving a first request message (104) from a first device (101), where the first request message (104) includes a first address aligned with a first data length and a first size in a unit of the first data length; converting the first address into a second address aligned with a second data length, where the second data length is greater than the first data length; converting the first size into a second size in a unit of the second data length; and sending a second request message (105) to a second device (103), where the second request message (105) includes the second address and the second size. Based on the data processing method, format conversion is performed on a processing request, so that the processing request can be easily switched between different hardware, to improve overall processing efficiency.

公开(公告)号：EP4322016A1

公开(公告)日：2024-02-14

申请号：EP22799222.9

申请日：2022-05-04

Applicant: Lemon Inc.

Inventor： CHEN, Yimin ,  LU, Shan ,  ZHANG, Junmou ,  ZHANG, Chuang ,  CHENG, Yuanlin ,  WANG, Jian

IPC: G06F15/17 ,  G06F13/36

Abstract: Disclosed are an integrated circuit, and a data processing apparatus and method. The integrated circuit comprises: a processor circuit and an accelerator circuit. The processor circuit comprises a processor, a first data storage area and a first data input/output interface. The accelerator circuit comprises an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit performs information interaction with the first data storage area, thereby reducing congestion on a processor bus, and improving application service quality.