公开(公告)号：EP1157298A1

公开(公告)日：2001-11-28

申请号：EP00917607.4

申请日：2000-02-01

Applicant: Light and Sound Design, Ltd.

Inventor： HUNT, Mark, A. ,  HEWLETT, William, E. ,  CLARKE, Ian ,  KNOBEL, Kille ,  FINDLEY, Drew ,  HOLT, Jonathan, C. ,  VARIN, Christopher

IPC: G02B26/00

CPC classification number: G09G5/363 ,  G02B26/0841 ,  G09G3/346 ,  G09G2340/10 ,  G09G2360/121

Abstract: A gate array schematic of this alternate embodiment in which a transfer controller (1106) is part of the FPGA. A transparency device (1100) which calculates values associated with transparency. A dual-port RAM (1102) which receives the VLIW at one port thereof, and outputs that value to a multiplexer (1104), which output it as a 32 bit signal used by a CPU/DSP (1105). The transfer controller (1106) is controlled directly by the CPU data received on line (1105). The transfer controller (1106) can have two lists of parameters (1110 and 1112), each 64 bits in width. These values are received on the list receivers.