公开(公告)号：EP1995876A1

公开(公告)日：2008-11-26

申请号：EP08156185.4

申请日：2008-05-14

Applicant: M/A-COM Inc.

Inventor： Perraud, Laurent Claude

IPC: H03M1/64

CPC classification number: H03M1/64

Abstract: An analog to digital converter (100) is provided that first converts an analog input voltage (Vin+, Vin-) into first (clk+) and second (clk-, clkref) periodic signals having a phase difference there between that is a function of the analog input voltage. The first periodic signal (clk+) is introduced into a forward direction data path through a series of consecutive delay cells so that the first periodic signal propagates through the cells via the first series of delay elements (111 1 -111 2n ) in a first direction. The second periodic signal (clk-, clkref) is introduced into a reverse direction data path through the same series of delay cells so that the second periodic signal propagates through the cells via the second series of delay elements (112 1 -112 2n ) in an opposite direction. Using the second periodic signal (clk-, clkref) to latch the first periodic signal (clk+) in each cell so as to generate an output signal for each cell, said output signals of said cells collectively indicating a unique cell (105 1 -105 2 n ) in which the leading edges of corresponding pulses in the first and second directions met. The outputs of the cells are decoded to generate a digital binary output value.

Abstract translation: 提供了一种模拟数字转换器（100），其首先将模拟输入电压（Vin +，Vin-）转换成具有相位差的第一（clk +）和第二（clk-，clkref）周期信号， 模拟输入电压。 第一周期信号（clk +）通过一系列连续延迟单元被引入到正向数据路径中，使得第一周期信号经由第一系列延迟元件（111 1 -111 2n）在第一方向上传播通过单元 。 将第二周期信号（clk-，clkref）通过相同的延迟单元序列引入反向数据路径，使得第二周期信号经由第二系列延迟元件（112 1 -112 2n）在单元中传播 相反的方向。 使用第二周期信号（clk-，clkref）来锁存每个单元中的第一周期信号（clk +），以便产生每个单元的输出信号，所述单元的所述输出信号共同指示唯一的单元（105 1 -105 2 n），其中在第一和第二方向上的相应脉冲的前沿被满足。 单元的输出被解码以产生数字二进制输出值。