公开(公告)号：WO1997039575A2

公开(公告)日：1997-10-23

申请号：PCT/US1997006202

申请日：1997-04-14

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  SAVOYE, Eugene, D. ,  WAXMAN, Allen, M. ,  REICH, Robert, K. ,  BURKE, Barry, E. ,  GREGORY, James, A. ,  McGONAGLE, William, H. ,  LOOMIS, Andrew, H. ,  KOSICKI, Bernard, B. ,  MOUNTAIN, Robert, W. ,  GOVE, Alan, N. ,  FAY, David, A. ,  CARRICK, James, E.

IPC: H04N05/335

CPC classification number: H04N5/20 ,  H04N5/335

Abstract: An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port (14), a charge-coupled imaging device (16a), an analog signal processor (24), and an analog-to-digital processor (A/D) (26). The A/D (26) digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor (28) is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B. The output image frame sequence is characterized by noise-limited resolution of at least a minimum number, NM, of line pairs per millimeter, referred to the charge-coupled imaging device pixel array, in an imaged scene as a function of illuminance of the input light impinging the charge-coupled imaging device pixels.

Abstract translation: 提供一种成像系统，用于对场景进行成像，以每秒至少约25幅图像帧的帧速率R产生场景的图像序列序列。 该系统包括光输入端口（14），电荷耦合成像装置（16a），模拟信号处理器（24）和模拟数字处理器（A / D）（26）。 A / D（26）将放大的像素信号数字化，以产生数字图像信号，该数字图像信号被格式化为多个数字像素值中的每一个的一系列图像帧，并具有由多个数字位表示的数字像素值的动态范围， B，其中B大于8.提供数字图像处理器（28）用于处理图像帧序列中的数字像素值以产生代表成像场景的帧速率R的输出图像帧序列， 不超过约1 / R的等待时间和由数字比特数D表示的图像帧像素值的动态范围，其中D小于B.输出图像帧序列的特征在于噪声限制分辨率为 作为影响电荷耦合的成像装置像素的输入光的照度的函数的成像场景中的称为电荷耦合成像装置像素阵列的每毫米线对的最小数目NM。

公开(公告)号：WO1997020351A1

公开(公告)日：1997-06-05

申请号：PCT/US1996018475

申请日：1996-11-18

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  SAVOYE, Eugene, D. ,  BURKE, Barry, E. ,  TONRY, John

IPC: H01L29/768

CPC classification number: H01L29/76858 ,  H01L27/1464 ,  H01L27/14831 ,  H01L29/1062

Abstract: A multidirectional charge transfer device (100) configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates (108), each of which is arranged in a first portion of each charge storage region, a plurality of second gates (114), each of which is arranged in a second portion of each charge storage region, a plurality of third gates (120), each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates (124), each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

Abstract translation: 一种配置在电荷存储介质中的多向电荷转移装置（100）。 该装置包括电荷存储区域的阵列。 每个所述电荷存储区域包括多个第一栅极（108），每个栅极布置在每个电荷存储区域的第一部分中，多个第二栅极（114），每个第二栅极布置在 每个电荷存储区域，每个电荷存储区域的第三部分中布置有多个第三栅极（120），以及多个第四栅极（124），每个栅极布置在每个电荷存储区域的第四部分中 电荷存储区域。 多个栅极和电荷存储区被配置为限定相对于彼此非共线的至少三个双向电荷传输路径。 多个栅极被顺序地偏置以沿着所述双向电荷转移路径之一建立电荷转移，并形成阻挡电位以在剩余电荷转移路径中进行电荷转移。

公开(公告)号：WO1998009334A1

公开(公告)日：1998-03-05

申请号：PCT/US1997014638

申请日：1997-08-20

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  REICH, Robert, K. ,  SAVOYE, Eugene, D. ,  KOSICKI, Bernard, B.

IPC: H01L27/148

CPC classification number: H01L29/76833 ,  H01L27/1464 ,  H01L31/1126

Abstract: A charge modulation device having a semiconductor region of a first conductivity type. An epitaxial layer of second conductivity type is provided on a portion of the semiconductor region so as to define an FET channel region. A first epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET drain region, the first epitaxial region being electrically isolated from the semiconductor region. A second epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET source region, the second epitaxial region being electrically isolated from the semiconductor region. A third epitaxial region of the first conductivity type or a metal oxide semiconductor is provided to the channel region between the source and drain regions.

Abstract translation: 一种具有第一导电类型的半导体区域的电荷调制装置。 在半导体区域的一部分上设置第二导电类型的外延层，以限定FET沟道区。 第二导电类型的第一外延区域设置成与外延层相邻并与外延层接触，以便限定FET漏区，该第一外延区域与半导体区域电绝缘。 第二导电类型的第二外延区域被设置为与外延层相邻并与外延层接触，以限定FET源极区域，第二外延区域与半导体区域电隔离。 第一导电类型的第三外延区域或金属氧化物半导体被提供给源区和漏区之间的沟道区。

公开(公告)号：WO1993011568A1

公开(公告)日：1993-06-10

申请号：PCT/US1992010369

申请日：1992-12-02

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  REICH, Robert, K. ,  KOSICKI, Bernard, B. ,  SAVOYE, Eugene, D.

IPC: H01L29/796

CPC classification number: H01L29/1091 ,  H01L27/14831

Abstract: A charge-coupled device having an array of pixel elements formed in a substrate (22) which device is operable in a first state to expand (25A) the depletion well regions of each pixel element into the substrate for storing incoming photoelectrons therein and in a second state to contract (25B) the expanded depletion well regions to prevent storage of photoelectrons in the contracted depletion well regions.

Abstract translation: 一种具有形成在衬底（22）中的像素元件阵列的电荷耦合器件，该器件可在第一状态下操作，以将每个像素元件的耗尽阱区扩展（25A）到衬底中，用于存储入射光电子，并且在 第二国承包（25B）扩大的耗尽井区域，以防止光电子在承包的耗尽井区域中储存。