公开(公告)号：WO1996002067A1

公开(公告)日：1996-01-25

申请号：PCT/US1995008575

申请日：1995-07-10

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  SCOTT, Michael, C. ,  CUCHIARO, Joseph, D.

IPC: H01L21/3205

CPC classification number: H01L27/11502 ,  C04B35/4682 ,  C04B35/6264 ,  C04B2235/3213 ,  C04B2235/3224 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3243 ,  C04B2235/3268 ,  C04B2235/441 ,  C04B2235/449 ,  C04B2235/72 ,  C23C16/4412 ,  C23C16/448 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/1216 ,  C23C18/1275 ,  C23C18/1295 ,  C23C18/14 ,  C30B7/00 ,  C30B29/68 ,  H01C7/1013 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/10805 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60

Abstract: A xylene exchange (P44) is performed on a stock solution of BST of greater than 99.999 % purity dissolved in methoxyethanol, and a carboxylate of a dopant metal, such as magnesium 2-ethylhexanoate is added to form a precursor. The precursor is spun (P45) on a first electrode (14), dried (P46) at 400 DEG C for 2 minutes, then annealed (P47) at 750 DEG C to 800 DEG C for about an hour to form a layer (15) of accurately doped BST. A second electrode (16) is deposited (P48), patterned (P49), and annealed (P50) at between 750 DEG C to 800 DEG C for about 30 minutes. Excellent leakage current results if the dopant is magnesium of about 5 % molarity. For other dopants, such as Mg, Nb, Y, Bi, and Sn the preferred dopant range is 0.2 % to 0.3 % molarity. The magnesium-doped material is used as a buffer layer (25, 27) between the electrodes (24, 28) and BST dielectric (26) of an undoped BST capacitor (20).

Abstract translation: 对溶解在甲氧基乙醇中的纯度大于99.999％的BST的原液进行二甲苯交换（P44），加入2-乙基己酸镁等掺杂剂金属的羧酸盐，形成前体。 将前体在第一电极（14）上旋转（P45），在400℃下干燥（P46）2分钟，然后在750℃至800℃下退火（P47）约1小时以形成层（15 ）精确掺杂的BST。 在750℃至800℃下沉积第二电极（P48），图案化（P49）和退火（P50）约30分钟。 如果掺杂剂为约5％摩尔浓度的镁，则会产生优异的漏电流。 对于其他掺杂剂如Mg，Nb，Y，Bi和Sn，优选的掺杂剂范围为0.2％至0.3％摩尔浓度。 镁掺杂材料用作未掺杂的BST电容器（20）的电极（24,28）和BST电介质（26）之间的缓冲层（25,27）。

公开(公告)号：WO1996001493A1

公开(公告)日：1996-01-18

申请号：PCT/US1995008296

申请日：1995-06-30

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  SCOTT, Michael, C.

IPC: H01L21/3205

CPC classification number: H01L27/11502 ,  C23C18/1216 ,  C23C18/1295 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60

Abstract: A method for fabricating an integrated circuit capacitor (10, 20, 30) having a dielectric layer (15, 26, 37) comprising BST with excess A-site and B-site materials such as barium and titanium added. An organometallic or metallic soap precursor solution is prepared (P42) comprising a stock solution of BST of greater than 99.999 % purity blended with excess A-site and B-site materials such as barium and titanium such that the barium is in the range of 0.01-100 mol %, and such that the titanium is in the range of 0.01-100 mol %. A xylene exchange (P44) is then performed to adjust the viscosity of the solution for spin-on application to a substrate. The precursor solution is spun on a first electrode (P45), dried (P46) at 400 DEG C for 2 to 10 minutes, then annealed (P47) at 650 DEG C to 800 DEG C for about an hour to form a layer of BST with excess titanium. A second electrode is deposited (P48), patterned (P49), and annealed at between 650 DEG C to 800 DEG C for about 30 minutes. The resultant capacitor (10, 20, 30) exhibits an enlarged dielectric constant with little change in leakage current.

Abstract translation: 一种用于制造集成电路电容器（10,20,30）的方法，该集成电路电容器具有包含BST的介电层（15,26,37），该BST具有过量的A位和B位的材料如钡和钛。 制备有机金属或金属皂前体溶液（P42），其包含与超过99.99％纯度的BST的储备溶液混合的过量A位和B位物质如钡和钛，使得钡在0.01 -100摩尔％，并且使得钛在0.01-100摩尔％的范围内。 然后进行二甲苯交换（P44）以调节溶液的粘度，以便旋涂到基底上。 将前体溶液在第一电极（P45）上旋转，在400℃下干燥（P46）2至10分钟，然后在650℃至800℃退火（P47）约1小时以形成BST层 与多余的钛。 沉积第二电极（P48），图案化（P49），并在650℃至800℃下退火约30分钟。 所得到的电容器（10,20,30）的介电常数增大，漏电流几乎没有变化。

公开(公告)号：WO1998011603A1

公开(公告)日：1998-03-19

申请号：PCT/US1997014452

申请日：1997-08-18

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  DERBENWICK, Gary, F. ,  MCMILLAN, Larry, D. ,  SOLAYAPPAN, Narayan ,  SCOTT, Michael, C. ,  PAZ DE ARAUJO, Carlos, A. ,  HAYASHI, Shinichiro

IPC: H01L21/316

CPC classification number: H01L21/31691 ,  C23C18/1216 ,  C23C18/1225

Abstract: A precursor liquid comprising several metal 2-ethylhexanoates, such as strontium, tantalum and bismuth 2-ethylhexanoates, in a xylenes/methyl ethyl ketone solvent is prepared, a substrate (5, 858) is placed within a vacuum deposition chamber (2), a small amount of hexamethyl-disilazane is added to the precursor liquid, is misted, and the mist is flowed into the deposition chamber to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film (506, 860) of a layered superlattice material, such as strontium bismuth tantalate, on the substrate. Then an integrated circuit (600, 850) is completed to include at least a portion of the layered superlattice material film in a component (604, 872) of the integrated circuit.

Abstract translation: 制备在二甲苯/甲基乙基酮溶剂中包含若干金属2-乙基己酸酯如锶，钽和2-乙基己酸铋的前体液体，将基材（5,858）置于真空沉积室（2）内， 少量的六甲基二硅氮烷被加入到前体液体中，被雾化，并且雾气流入沉积室以将一层前体液体沉积在基底上。 将液体干燥，烘烤和退火，以在衬底上形成层状超晶格材料（例如钽酸锶锶）的薄膜（506,860）。 然后，完成集成电路（600,850），以将集成电路的部件（604,872）中的至少一部分分层超晶格材料膜包括在内。

公开(公告)号：WO1997033310A1

公开(公告)日：1997-09-12

申请号：PCT/US1997003046

申请日：1997-03-04

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  HAYASHI, Shinichiro ,  MCMILLAN, Larry, D. ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A.

IPC: H01L21/3205

CPC classification number: H01L21/31691

Abstract: A liquid primer is misted, flowed into a deposition chamber (2) and deposited on a substrate (5). A liquid precursor (64) is misted, flowed into a deposition chamber (2) and deposited on the substrate (5). The primer and precursor are dried to form a solid thin film, which is then annealed to form a part of an electronic component (1112) in an integrated circuit (1110), such as the dielectric (1130) in a memory cell. The primer is a solvent, and the precursor includes a metal carboxylate, a metal alkoxide, or a metal alkoxycarboxylate in a precursor solvent. Preferably, the primer and the precursor solvent are the same solvent, such as 2-methodyethanol, xylenes, n-butyl acetate or hexymethyl-disilazane.

Abstract translation: 液体底漆被雾化，流入沉积室（2）并沉积在基底（5）上。 液体前体（64）被雾化，流入沉积室（2）并沉积在基底（5）上。 将底漆和前体干燥以形成固体薄膜，然后将其退火以在集成电路（1110）中形成电子部件（1112）的一部分，例如存储器单元中的电介质（1130）。 引物是溶剂，前体在前体溶剂中包括金属羧酸盐，金属醇盐或烷氧基羧酸金属盐。 优选地，底漆和前体溶剂是相同的溶剂，例如2-甲醇，二甲苯，乙酸正丁酯或羟甲基 - 二硅氮烷。

公开(公告)号：WO1997027346A1

公开(公告)日：1997-07-31

申请号：PCT/US1997001055

申请日：1997-01-24

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  HAYASHI, Shinichiro ,  McMILLAN, Larry, D. ,  PAZ DE ARAUJO, Carlos, A.

IPC: C23C26/02

CPC classification number: C23C18/1216 ,  B05D1/00 ,  B05D1/60 ,  B05D3/0493 ,  B05D3/062 ,  B05D3/065 ,  C23C8/10 ,  C23C16/4412 ,  C23C16/448 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/14 ,  C23C26/02 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L41/1871 ,  H01L41/317 ,  H05K3/105

Abstract: UV radiation is applied to a substrate in a deposition chamber to desorb water and other contaminates from it. A liquid precursor is misted, flowed into the deposition chamber and deposited on a substrate while UV radiation is applied to the mist. The film of liquid on the substrate is dried and annealed on the substrate while the UV radiation is applied to form a solid thin film of a metal oxide. The thin film is then incorporated into an electronic device of an integrated circuit fabricated on the substrate. The application of UV radiation to both the mist during deposition and the thin film after deposition significantly increases the quality of the resulting integrated circuits. The process has been found to be particularly excellent for making BST, strontium bismuth tantalate, and strontium bismuth niobate.

Abstract translation: 将UV辐射施加到沉积室中的基底以从其中解吸水和其它污染物。 液体前体被雾化，流入沉积室并沉积在基底上，同时将紫外线辐射施加于雾。 将衬底上的液体膜干燥并在衬底上退火，同时施加UV辐射以形成金属氧化物的固体薄膜。 然后将薄膜并入到在衬底上制造的集成电路的电子器件中。 在沉积期间将UV辐射施加到雾和沉积后的薄膜显着增加了所得到的集成电路的质量。 已经发现该方法对于制备BST，钽酸锶锶和铌酸铋锶特别优异。

公开(公告)号：WO1997007546A1

公开(公告)日：1997-02-27

申请号：PCT/US1996013310

申请日：1996-08-19

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos

IPC: H01L29/51

CPC classification number: C23C18/14 ,  C04B35/62227 ,  C23C16/448 ,  C23C16/45561 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1295 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/10805 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L29/78391

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxyde superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract translation: MIS器件（20）包括半导体衬底（22），氮化硅缓冲层（24），铁电金属氧化物超晶格材料（26）和贵金属顶电极（28）。 层状超晶格材料（26）优选为钽酸锶锶，铌酸铋锶或钽酸铋铌钽酸锶。 根据优选的方法构造器件，其包括在沉积层状超晶格材料之前在半导体衬底上形成氮化硅。 层状超晶格材料优选使用液体聚氧化烷基化的金属有机前体沉积，其在加热前体溶液时自发产生层状超晶格。 在前体液体的干燥期间的紫外线曝光赋予最终晶体C轴取向，并且导致改善的薄膜电性能。

公开(公告)号：WO1995025340A1

公开(公告)日：1995-09-21

申请号：PCT/US1995003254

申请日：1995-03-16

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  SCOTT, Michael, C. ,  UEDA, Toshiyuki

IPC: H01L21/3205

CPC classification number: C23C18/1225 ,  C23C18/1216 ,  H01L21/31691 ,  H01L28/55

Abstract: A silicone nitride barrier layer (12) is deposited on a gallium arsenide substrate (11) to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer (14) is deposited on the barrier layer. A first electrode (16) comprising an adhesion layer (18) and a second layer (20) is formed on the stress reduction layer. An essentially anhydrous alkoxycarboxylate liquid precursor is prepared, just before use a solvent exchange step is performed, then the precursor is spun on the first electrode, dried at 400 DEG C, and annealed at between 600 DEG C and 850 DEG C to form a BST capacitor dielectric (22). A second electrode (24) is deposited on the dielectric and annealed.

Abstract translation: 将氮化硅阻挡层（12）沉积在砷化镓衬底（11）上，以防止随后的加热步骤中衬底的蒸发。 二氧化硅应力减少层（14）沉积在阻挡层上。 在应力降低层上形成包括粘合层（18）和第二层（20）的第一电极（16）。 制备基本上无水的烷氧基羧酸盐液体前体，刚好在使用前进行溶剂交换步骤，然后将前体在第一电极上纺丝，在400℃下干燥，并在600℃和850℃之间退火以形成BST 电容电介质（22）。 第二电极（24）沉积在电介质上并退火。

公开(公告)号：WO1997034320A1

公开(公告)日：1997-09-18

申请号：PCT/US1997004185

申请日：1997-03-14

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  MCMILLAN, Larry, D. ,  SCOTT, Michael, C. ,  PAZ DE ARAUJO, Carlos, A. ,  OTSUKI, Tatsuo ,  HAYASHI, Shinichiro

IPC: H01L21/316

CPC classification number: H01L21/316 ,  B05D1/00 ,  B05D1/60 ,  B05D3/0493 ,  C23C16/4412 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/1212 ,  C23C18/1287 ,  C23C18/14 ,  C23C26/02 ,  C30B7/00 ,  C30B29/68 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L41/316 ,  H05K3/105

Abstract: A precursor liquid (64) comprising silicon in a xylene solvent is prepared, a substrate (5, 71) is placed within a vacuum deposition chamber (2), the precursor liquid is misted, and the mist (66) is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film (1224, 77) of silicon dioxide or silicon glass on the substrate. Then an integrated circuit (100) is completed to include at least a portion of the silicon dioxide or silicon glass layer as an insulator (77) for an electronic device (76) in the integrated circuit.

Abstract translation: 制备在二甲苯溶剂中含硅的前体液体（64），将基材（5,71）放置在真空沉积室（2）内，使前体液体雾化，并将雾（66）流入沉积物 同时将室保持在环境温度下，以将一层前体液体沉积在基底上。 将液体干燥，烘烤和退火，以在基底上形成二氧化硅或硅玻璃的薄膜（1224,77）。 然后，完成集成电路（100）以将至少一部分二氧化硅或硅玻璃层作为用于集成电路中的电子器件（76）的绝缘体（77）。

公开(公告)号：WO1997033013A1

公开(公告)日：1997-09-12

申请号：PCT/US1997003393

申请日：1997-03-04

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  HAYASHI, Shinichiro ,  MCMILLAN, Larry, D. ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A.

IPC: C23C26/02

CPC classification number: H01L21/02197 ,  B05D1/00 ,  B05D1/60 ,  B05D3/0493 ,  B05D3/062 ,  B05D3/065 ,  C23C8/10 ,  C23C16/4412 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/12 ,  C23C18/1216 ,  C23C18/1287 ,  C23C18/14 ,  C23C26/02 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/02282 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L41/1871 ,  H01L41/314 ,  H05K3/105

Abstract: A substrate (5) is located within a deposition chamber (2), the substrate defining a substrate plane. A barrier plate (6) is disposed in spaced relation above the substrate and substantially parallel thereto, the area of said barrier plate in a plane parallel to said substrate being substantially equal to said area of said substrate in said substrate plane, i.e. within 10 % of said substrate area. The barrier plate has a smoothness tolerance of 5 % of the average distance between said barrier plate and said substrate. A mist (66) is generated, allowed to settle in a buffer chamber (42), filtered through a 1 micron filter (33), and flowed into the deposition chamber between the substrate and barrier plate to deposit a liquid layer on the substrate. The liquid is dried to form a thin film (1130) of solid material on the substrate, which is then incorporated into an electrical component (1112) of an integrated circuit (1110).

Abstract translation: 衬底（5）位于沉积室（2）内，衬底限定衬底平面。 阻挡板（6）以基板间隔开的关系设置并且基本上平行于其上，所述阻挡板在与所述基板平行的平面中的面积基本上等于所述基板平面中的所述基板的面积，即在10％ 的所述衬底区域。 阻挡板具有所述阻挡板和所述基板之间的平均距离的5％的平滑度公差。 产生雾（66），允许沉淀在缓冲室（42）中，通过1微米过滤器（33）过滤，并流入基板和阻挡板之间的沉积室，以在基板上沉积液体层。 将液体干燥以在基板上形成固体材料的薄膜（1130），然后将其并入集成电路（1110）的电气部件（1112）中。

公开(公告)号：WO1996041375A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009100

申请日：1996-06-06

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  CUCHIARO, Joseph, D.

IPC: H01L23/532

CPC classification number: H01L27/11502 ,  H01L23/53242 ,  H01L23/53252 ,  H01L28/55 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin-film ferroelectric capacitor (20) includes a bottom electrode structure (26) having an adhesion metal layer (36) and a noble metal portion (38). The electrode (26) is deposited over a thin-film buffer layer (24), which contains a layered superlattice material. The buffer layer is interposed between a substrate (22) and the bottom electrode (26). A process of manufacture includes deposition of a liquid precursor on the substrate (22) prior to formation of the bottom electrode (26).

Abstract translation: 薄膜强电介质电容器（20）包括具有粘附金属层（36）和贵金属部分（38）的底部电极结构（26）。 电极（26）沉积在包含层状超晶格材料的薄膜缓冲层（24）上。 缓冲层介于衬底（22）和底电极（26）之间。 一种制造方法包括在形成底部电极（26）之前在基底（22）上沉积液体前体。