公开(公告)号：WO2022256153A1

公开(公告)日：2022-12-08

申请号：PCT/US2022/028767

申请日：2022-05-11

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GOYAL, Sanjay ,  CARR, Larrie Simon ,  BAILEY, Patrick

IPC: G06F13/16

Abstract: System and method for analyzing CXL flits at read bypass detection logic (115) to identify bypass memory read requests (108) and transmitting the identified bypass memory read requests (108) over a read request bypass path (120) directly to a transaction/ application layer (135) of the CXL memory controller (100), wherein the read request bypass path (120) does not include an arbitration/ multiplexing layer (125) and a link layer (130) of the CXL memory controller (100), thereby reducing the latency inherent in a CXL memory controller (100).